Microprocessor, Computer, Organization, and Architecture

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The 8085 is an 8-bit microprocessor with an 8-bit data bus and a 16-bit address bus, letting it address up to 64 KB of memory.

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8085 internal architecture includes the ALU, the Accumulator (A), general-purpose register pairs (B-C, D-E, H-L), the Program Counter (PC), the Stack Pointer (SP), a Flag register (Sign, Zero, Auxiliary Carry, Parity, Carry), an instruction register/decoder, and timing & control circuitry.

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The 8085 supports 5 hardware interrupts — TRAP, RST 7.5, RST 6.5, RST 5.5, INTR — and operates at clock speeds up to a few MHz.

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8085 instruction formats may be 1-byte, 2-byte, or 3-byte, consisting of an opcode plus zero, one, or two operand bytes.

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8085 addressing modes: Immediate (operand given in the instruction), Register (operand in a register), Direct (operand's memory address given directly), Indirect (address held in a register pair, e.g. HL), and Implied/Implicit (operand implied by the opcode itself, e.g. CMA).

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The 8086 is a 16-bit microprocessor with a 16-bit data bus and a 20-bit address bus, able to address 1 MB of memory using segmented memory (Code, Data, Stack, and Extra Segment registers: CS, DS, SS, ES).

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The 8086 is internally split into two functional units working in parallel (pipelining): the Bus Interface Unit (BIU), which fetches instructions and manages addresses/data on the bus, and the Execution Unit (EU), which decodes and executes instructions.

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8086 addressing modes: Register, Immediate, Direct, Register Indirect, Based, Indexed, Based-Indexed, and Relative Based-Indexed — more modes than the 8085 offers.

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**EXE programs** can have multiple segments (code/data/stack/extra), can exceed 64 KB, are relocatable, and need a linker; **COM programs** use one combined segment, are limited to 64 KB, are non-relocatable, and always load at offset 0100H.

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Assembling: the Assembler translates the source program (.ASM, in mnemonics) into an object file (.OBJ) containing machine code and unresolved references.

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Linking: the Linker combines one or more object modules plus any required library routines, resolving cross-references, to produce a single executable file (.EXE/.COM).

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Executing: the Loader loads the executable into memory and transfers control to it so the CPU can run the program. Order: Assembler → Linker → Loader.

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**One-pass assembler** scans the source only once and handles forward references using back-patching (faster, more complex logic); **two-pass assembler** scans twice — Pass 1 builds a complete symbol table, Pass 2 generates machine code using it (simpler logic, no back-patching needed).

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Memory devices are broadly classified as Primary (registers, cache, RAM, ROM — directly CPU-accessible) and Secondary (hard disk, optical disk, tape — larger, slower, non-volatile).

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The memory hierarchy arranges storage from fastest/smallest/costliest at the top (Registers) down through Cache, Main Memory (RAM), to the slowest/largest/cheapest at the bottom (Secondary storage).

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**Memory-Mapped I/O** shares the same address space as memory and uses ordinary memory-reference instructions (e.g. MOV), which reduces available memory address space; **I/O-Mapped (Isolated) I/O** uses a separate dedicated address space and special I/O instructions (e.g. IN, OUT), preserving the full memory address space.

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A parallel interface transmits multiple bits of data simultaneously over separate lines, giving high speed over short distances.

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The Programmable Peripheral Interface (PPI), e.g. Intel 8255, provides three programmable 8-bit I/O ports (Port A, Port B, Port C), configurable as Mode 0 (simple I/O, no handshaking), Mode 1 (handshake-based I/O with strobe/ready signals), or Mode 2 (bidirectional bus, Port A only).

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A serial interface transmits data one bit at a time over a single line — slower than parallel but needs far fewer wires, making it suited to long-distance links. Common serial standards include RS-232 and USB.

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**Synchronous transmission**: sender and receiver share a common clock signal, data sent as large blocks/frames, faster with lower overhead, used for high-speed data links; **Asynchronous transmission**: no shared clock, timing recovered from start/stop bits per character, simpler hardware but more overhead, typical of UART-based communication (e.g. RS-232).

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Direct Memory Access (DMA) allows a peripheral device to transfer data directly to/from main memory without CPU intervention for every byte, greatly increasing transfer speed and freeing the CPU for other work.

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A DMA controller (e.g. Intel 8257) manages the transfer: it requests control of the system bus from the CPU using HOLD/HLDA handshaking signals, then directly drives the address/data bus during the transfer.

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DMA transfer modes include Burst mode (transfers an entire data block at once, holding the bus until done) and Cycle-stealing mode (transfers one word at a time, periodically stealing individual bus cycles from the CPU).

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An interrupt is a signal that temporarily suspends the CPU's normal instruction sequence so it can respond to a higher-priority event, after which execution resumes where it left off.

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The Interrupt Service Routine (ISR) is the special routine executed in response to an interrupt; once the ISR finishes, control returns to the interrupted program.

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8085 interrupts: 5 hardware interrupts — TRAP, RST 7.5, RST 6.5, RST 5.5, INTR — with priority order TRAP highest, INTR lowest; TRAP cannot be masked, the others can be selectively masked; software interrupts are triggered via RST 0–7 instructions.

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8086 interrupts: split into maskable (`INTR`) and non-maskable (`NMI`); uses an Interrupt Vector Table of 256 entries (4 bytes each), located at memory addresses 0000:0000 onward; software interrupts via the INT instruction (e.g. INT n).

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**Real (true) parallelism** — multiple processors genuinely execute multiple instructions/tasks at exactly the same instant; **Pseudo-parallelism** — a single processor rapidly switches between multiple tasks (time-sharing/multitasking), creating the illusion of simultaneous execution though only one task actually runs at any given instant.

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Flynn's Classification: SISD (Single Instruction, Single Data — traditional uniprocessor), SIMD (Single Instruction, Multiple Data — vector/array processors, GPUs), MISD (Multiple Instruction, Single Data — rare, fault-tolerant systems), MIMD (Multiple Instruction, Multiple Data — multiprocessor/multicomputer systems).

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Parallelism granularity levels: Instruction level (fine-grained, e.g. pipelining, superscalar execution), Thread level (multiple threads of the same process sharing its memory space), and Process level (multiple independent processes, each with its own separate memory space).

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A deadlock occurs when a set of processes are each waiting indefinitely for a resource held by another process in the set, so none can proceed.

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Four necessary conditions for deadlock: Mutual exclusion (resources can't be shared), Hold and wait (a process holds one resource while waiting for another), No preemption (resources can't be forcibly taken away), and Circular wait (a closed chain of processes each waiting on the next).

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Features of a typical operating system: multitasking/multiprogramming, multi-user support, process & memory management, file management, device management, and security.

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Hardwired control generates control signals using fixed combinational logic circuits: very fast, but difficult to modify (requires redesigning hardware) — used where speed is critical, e.g. RISC processors.

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Microprogrammed control stores control signals as microinstructions in a control memory (microprogram): relatively slower (each micro-operation is fetched from control memory), but easy to modify (just change the microprogram) — used where flexibility is valued, e.g. complex CISC instruction sets.

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Control memory stores the microinstructions (control words) that specify which control signals must be activated for each micro-operation.

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Addressing/sequencing of microinstructions determines which microinstruction runs next: sequential (next in line), branch (conditional jump), or subroutine call within the microprogram.

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**Horizontal** microinstruction format: each bit directly controls one signal — wide words, little/no decoding needed, fast, but uses more control-memory space; **Vertical** microinstruction format: control information is encoded into compact fields requiring decoding before use — narrower words, saves memory, but slightly slower.

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CPU structure comprises the ALU (arithmetic/logic), the Control Unit (sequencing & signal generation), Registers (fast internal storage), and an internal bus connecting them.

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Instruction formats are classified by number of addresses/operands specified: zero-address (stack-based, operands implied), one-address (uses an accumulator), two-address, and three-address instructions.

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Addressing modes specify how an instruction's operand address is determined: Immediate, Direct, Indirect, Register, Register Indirect, Displacement/Indexed, and Relative.

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Data transfer & manipulation instructions include data movement (MOV/LOAD/STORE), arithmetic (ADD, SUB, MUL, DIV), logical (AND, OR, XOR, NOT), and shift/rotate operations.

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**RISC**: small, simple, fixed-length instruction set; most instructions execute in a single clock cycle; fewer addressing modes; load/store architecture; relies heavily on efficient pipelining (e.g. ARM, MIPS). **CISC**: large, complex, variable-length instruction set; instructions may take multiple clock cycles; many addressing modes with operations acting directly on memory; pipelining is harder due to instruction complexity/variable length (e.g. Intel x86).

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Pipelining overlaps the execution of multiple instructions across stages (e.g. Fetch, Decode, Execute, Memory access, Write-back) to increase overall instruction throughput.

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Pipelines can suffer hazards: structural (hardware resource conflicts), data (an instruction needs a result not yet produced), and control (caused by branches changing the instruction flow).

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Arithmetic operations: addition and subtraction are typically performed using 2's complement representation; multiplication may use algorithms such as Booth's algorithm; division uses restoring/non-restoring division techniques.

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Logical operations: AND, OR, XOR, NOT, and shift/rotate operations manipulate data at the bit level.

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**Internal memory** (registers, cache, main memory/RAM) is directly accessible by the CPU, mostly volatile, very fast; **External memory** (hard disk, optical disk, tape) is not directly accessible by the CPU — data must first be brought into internal memory — and is non-volatile, slower, but much larger capacity and cheaper per byte.

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The memory hierarchy arranges storage from fastest/costliest/smallest (Registers → Cache → Main Memory) to slowest/cheapest/largest (Secondary storage), balancing speed, cost, and capacity.

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Cache memory is a small, very fast memory placed between the CPU and main memory to reduce the average memory access time, exploiting the principle of locality.

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Locality of reference: Temporal locality (recently accessed data is likely to be accessed again soon) and Spatial locality (data near a recently accessed location is likely to be accessed soon too).

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Cache design — size: a larger cache generally means a higher hit rate, but is costlier and can be slightly slower to search.

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Cache design — mapping function: Direct mapping (each block maps to exactly one cache line), Fully Associative (a block can go anywhere), Set-Associative (a block maps to any line within a specific set).

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Cache design — replacement algorithm: LRU (Least Recently Used), FIFO (First In First Out), LFU (Least Frequently Used), Random — decides which block to evict when the cache is full.

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Cache design — write policy: Write-through (updates cache and main memory together, simpler, more traffic) vs Write-back (updates cache only, main memory updated later, faster, more complex).

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Cache design — number of caches: single-level vs multi-level (L1, L2, L3); Unified cache (instructions + data together) vs Split cache (separate instruction and data caches).

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Write ability: RAM supports full read/write; ROM is mainly read-only (PROM/EPROM/EEPROM allow limited/special rewriting).

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Storage permanence: RAM is volatile (loses data without power); ROM and secondary storage are non-volatile (retain data without power).

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Composing memory refers to combining smaller memory chips/modules (using address decoding logic) to build a memory system of the desired total size and data-bus width for a system.

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Peripheral devices include input devices (keyboard, mouse, scanner), output devices (monitor, printer), and storage devices (disk drives).

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An I/O module (I/O interface) is the hardware that connects a peripheral to the system bus; it handles data buffering, reports device status, performs error detection, and manages address decoding so the CPU can address the device correctly.

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**Programmed I/O**: the CPU actively polls the device's status flag in a busy-wait loop until it is ready — high CPU involvement, tied up the whole time.

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**Interrupt-driven I/O**: the device signals the CPU with an interrupt only once it is ready; the CPU is free to do other work meanwhile — moderate CPU involvement.

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**DMA**: data is transferred directly between device and memory by a DMA controller, bypassing the CPU almost entirely — minimal CPU involvement, only at transfer setup/completion.

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A multiprocessor system uses two or more CPUs that share memory and other resources, cooperating to execute programs concurrently, which increases overall throughput and system reliability (fault tolerance if one processor fails).

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Interconnection structure — Bus-based (common/shared bus): all processors and memory modules connect to one shared bus; simple and low-cost, but the bus can become a bottleneck.

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Interconnection structure — Crossbar switch: every processor connects to every memory module through a dedicated switch matrix; very high performance but expensive/complex.

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Interconnection structure — Multistage network: multiple switching stages connect processors to memory modules, offering a balance between the low cost of a bus and the high performance of a crossbar.

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Processors communicate either via shared memory (a common memory area both can read/write) or message passing (explicit send/receive of messages, used when memory is not shared).

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Synchronization primitives — locks, semaphores, and barriers — coordinate concurrent access to shared resources and keep cooperating processors properly ordered, preventing race conditions