Data Communication, Computer Network and Organization

1

The OSI Model has 7 layers: Physical (bits, cables) → Data Link (frames, MAC) → Network (packets, IP) → Transport (segments, TCP/UDP) → Session → Presentation → Application.

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The TCP/IP Model has 4 layers: Network Access (Physical + Data Link), Internet (Network), Transport, Application (Session + Presentation + Application).

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Network devices by OSI layer: Hub = Layer 1 (Physical — broadcasts to all ports), Switch/Bridge = Layer 2 (Data Link — forwards by MAC address), Router = Layer 3 (Network — routes by IP address).

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MAC Address (Media Access Control) is a 48-bit hardware address burned into NIC. Format: AA:BB:CC:DD:EE:FF. Layer 2 switches forward frames based on MAC address tables.

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ARP (Address Resolution Protocol) resolves IP addresses to MAC addresses on a local network. Host broadcasts an ARP request; the target responds with its MAC. ARP is a Layer 2/3 boundary protocol.

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CSMA/CD (Carrier Sense Multiple Access with Collision Detection) is used in wired Ethernet (IEEE 802.3). Detects collisions after transmission begins, stops, and retransmits after a random backoff.

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CSMA/CA (Collision Avoidance) is used in wireless networks (IEEE 802.11 Wi-Fi). Avoids collisions by waiting for channel to be clear and using RTS/CTS handshake. Collisions cannot be detected in wireless.

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IEEE Standards: 802.3 = Ethernet (wired), 802.11 = Wi-Fi (wireless), 802.15 = Bluetooth, 802.16 = WiMAX.

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Framing (Data Link Layer): adds header (destination MAC, source MAC) and trailer (CRC for error detection) to form a frame. CRC (Cyclic Redundancy Check) detects transmission errors.

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Ethernet frame structure: Preamble (7B) | Start Frame Delimiter (1B) | Destination MAC (6B) | Source MAC (6B) | EtherType/Length (2B) | Data (46-1500B) | FCS/CRC (4B).

1

IPv4 uses 32-bit addresses (e.g., 192.168.1.1), supporting ~4.3 billion addresses. IPv6 uses 128-bit addresses (e.g., 2001:db8::1), with a virtually unlimited address space.

2

IP Address Classes (classful): Class A: 1.0.0.0–126.255.255.255 (first octet 1-126, /8 default), Class B: 128.0.0.0–191.255.255.255 (128-191, /16), Class C: 192.0.0.0–223.255.255.255 (192-223, /24), Class D: 224–239 (multicast), Class E: 240–255 (reserved/experimental).

3

Loopback address: 127.0.0.1 (localhost) — used for testing local network stack. Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16.

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Subnetting divides a network into smaller subnets using a subnet mask. CIDR notation: 192.168.1.0/24 means first 24 bits are network. Number of hosts = 2^(32-prefix) - 2.

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Routing Protocols: RIP (Routing Information Protocol) — distance-vector, metric = hop count, max 15 hops (16 = unreachable), uses Bellman-Ford. OSPF (Open Shortest Path First) — link-state, uses Dijkstra's algorithm, no hop limit, scales better. BGP — inter-AS (internet backbone).

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TCP (Transmission Control Protocol): connection-oriented, reliable delivery, ordered segments, flow control (sliding window), congestion control. Used for HTTP, FTP, email.

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UDP (User Datagram Protocol): connectionless, unreliable, no ordering guarantee, low overhead. Used for DNS, video streaming, VoIP, online gaming.

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TCP 3-Way Handshake: SYN → SYN-ACK → ACK. Client sends SYN; server responds SYN-ACK; client confirms with ACK. Connection established. 4-way termination: FIN → ACK → FIN → ACK.

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ICMP (Internet Control Message Protocol): used for error reporting and diagnostics. ping uses ICMP Echo Request/Reply. traceroute uses ICMP TTL Exceeded messages.

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A socket is the combination of IP address + Port number, uniquely identifying a network endpoint. A connection is identified by (source IP, source port, destination IP, destination port) — a 4-tuple.

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Well-known port numbers: HTTP=80, HTTPS=443, FTP=20 (data) / 21 (control), SSH=22, Telnet=23, SMTP=25, DNS=53, DHCP=67/68, POP3=110, IMAP=143.

2

DNS (Domain Name System) resolves domain names to IP addresses. Hierarchical: Root → TLD (.com, .np) → Authoritative name server. DNS uses UDP port 53 (TCP for zone transfers).

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DHCP (Dynamic Host Configuration Protocol) automatically assigns IP address, subnet mask, default gateway, and DNS server to hosts. DORA process: Discover → Offer → Request → Acknowledge.

4

Symmetric encryption uses the same key for encryption and decryption. Fast but key distribution is a problem. Examples: AES (Advanced Encryption Standard — 128/192/256-bit keys), DES (56-bit, obsolete), 3DES.

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Asymmetric encryption uses a public-private key pair. Encrypt with public key, decrypt with private key (or vice versa for signatures). Slow but solves key distribution. Examples: RSA, ECC, Diffie-Hellman (key exchange).

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Digital Signature: sender encrypts message hash with private key; receiver verifies with sender's public key. Provides authentication + integrity + non-repudiation. If signature verifies, message is authentic.

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PGP (Pretty Good Privacy) uses a combination of symmetric and asymmetric encryption for secure email. Uses the 'web of trust' model instead of a central CA.

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VPN (Virtual Private Network) creates an encrypted tunnel over a public network. Protocols: IPsec (Network layer), SSL/TLS (Application layer), PPTP (deprecated). Provides confidentiality and integrity.

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Firewall controls traffic based on rules (IP, port, protocol). Types: Packet filter (stateless, examines headers), Stateful inspection (tracks connection state), Application-layer firewall (deep packet inspection).

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Common attacks: DDoS (Distributed Denial of Service — overwhelm with traffic), Man-in-the-Middle (intercept communications), SQL Injection (malicious SQL in input), Phishing (fake websites/emails), ARP Spoofing (fake ARP replies).

1

Synchronous transmission sends data in continuous blocks with a shared clock. Efficient for large data transfers — no per-character overhead. The sender and receiver clocks are synchronized.

2

Asynchronous transmission sends one character at a time framed by start and stop bits. No shared clock needed. Start bit (0) signals beginning; stop bit(s) (1) mark the end. Simple but adds per-character overhead.

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ATM (Asynchronous Transfer Mode) uses fixed-size 53-byte cells (5-byte header + 48-byte payload). Designed for real-time traffic — fixed cell size guarantees bounded latency. Used in WAN backbones.

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Network evolution: X.25 (packet-switched, 1970s, low speed) → Frame Relay (faster, variable frames, 1980s) → ATM (fixed cells, QoS, 1990s) → MPLS (label switching, modern WAN).

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Socket Programming: A socket is an endpoint for communication. In TCP: socket() → bind() → listen() → accept() (server); socket() → connect() (client). Both then use send()/recv(). close() terminates.

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Server daemon is a background process that listens continuously for client connections on a well-known port. Examples: Apache httpd (port 80), sshd (port 22), mysqld (port 3306).

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`select()` / `poll()` system calls enable I/O multiplexing — monitoring multiple socket file descriptors simultaneously for readability/writability. Allows a single thread to handle multiple connections.

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Network Management SNMP (Simple Network Management Protocol): manages network devices. Components: Manager (collects data), Agent (runs on device), MIB (Management Information Base — database of device info). Uses UDP port 161/162.

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Quality of Service (QoS) mechanisms prioritize traffic. Differentiated Services (DiffServ) marks packets; IntServ reserves bandwidth (RSVP). Important for real-time traffic like VoIP.

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Network Address Translation (NAT) maps private IP addresses to a public IP. Allows multiple devices to share one public IP. Types: Static NAT (1:1), Dynamic NAT (pool), PAT/NAT Overload (many:1, most common in home routers).

1

The CPU (Central Processing Unit) consists of: CU (Control Unit — fetches and decodes instructions), ALU (Arithmetic Logic Unit — performs arithmetic and logical operations), Registers (fast on-chip storage).

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Instruction Cycle (fetch-decode-execute): Fetch (PC → MAR → memory → MDR → IR), Decode (CU decodes IR), Execute (ALU performs operation, result to register or memory).

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Key CPU registers: PC (Program Counter — address of next instruction), IR (Instruction Register — current instruction), MAR (Memory Address Register), MDR (Memory Data Register), ACC (Accumulator).

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Hardwired Control Unit: control signals generated by combinational logic circuits. Fast but inflexible — changing instruction set requires redesigning hardware. Used in RISC processors.

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Microprogrammed Control Unit: each machine instruction decoded into micro-operations stored in a control memory (microprogram store). Flexible — can modify instruction set by changing microcode. Used in CISC processors.

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RISC (Reduced Instruction Set Computer): simple, fixed-length instructions, large register set, load-store architecture (only load/store accesses memory), hardwired control. Examples: ARM, MIPS, RISC-V.

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CISC (Complex Instruction Set Computer): complex, variable-length instructions, few registers, memory operands allowed, microprogrammed control. Examples: x86, x86-64 (Intel/AMD).

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Pipelining overlaps execution of multiple instructions. Stages: IF → ID → EX → MEM → WB. Increases throughput. Pipeline hazards: Structural (resource conflict), Data (RAW, WAW, WAR dependencies), Control (branches).

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Flynn's Taxonomy classifies computers by instruction and data streams: SISD (single CPU), SIMD (GPU, vector processing), MISD (rare), MIMD (multiprocessors, multicore, distributed).

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System buses: Address bus (unidirectional — CPU to memory), Data bus (bidirectional — data transfer), Control bus (control signals — read/write/interrupt). Bus width determines addressable memory and data transfer width.

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Memory Hierarchy (fastest/smallest to slowest/largest): Registers → Cache (L1/L2/L3) → RAM (Main Memory) → Secondary Storage (SSD/HDD) → Tertiary (tape). Speed decreases, size and cost-per-bit decrease as you go down.

2

Cache Memory exploits temporal and spatial locality. Temporal: recently used data likely reused soon. Spatial: nearby memory locations likely accessed together. Cache hit = data found; cache miss = fetch from lower memory.

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Cache Mapping techniques: Direct mapping (each RAM block maps to ONE cache line — simple, but conflicts), Fully associative (block maps to ANY cache line — flexible, expensive), Set-associative (compromise — block maps to a set of lines).

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Cache replacement policies: LRU (Least Recently Used — evict oldest unused), FIFO (First In First Out), Random, LFU (Least Frequently Used). LRU is most commonly used for its effectiveness.

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DMA (Direct Memory Access): allows I/O devices to transfer data directly to/from RAM without CPU intervention. CPU initializes the DMA controller (source, destination, count), then continues other work. DMA controller raises interrupt when done.

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Programmed I/O (Polling): CPU repeatedly checks the device status register (busy-wait). Simple but wastes CPU cycles.

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Interrupt-driven I/O: device raises an interrupt when ready; CPU handles it via the Interrupt Service Routine (ISR). More efficient than polling — CPU does useful work between I/O events.

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Memory-mapped I/O: I/O device registers are mapped into the CPU's address space. Same instructions (load/store) used for both memory and I/O. Example: modern x86 systems.

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Isolated (Port-mapped) I/O: I/O devices use a separate address space with special instructions (IN/OUT in x86). Older approach, requires separate I/O bus.

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Virtual Memory: extends RAM using secondary storage (swap space). OS manages page table mapping virtual to physical addresses. Page fault = requested page not in RAM, must load from disk. TLB (Translation Lookaside Buffer) caches recent page table entries.