Computer Organization and Embedded System

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The CPU consists of the ALU (Arithmetic and Logic Unit), the Control Unit, registers, and internal buses that connect them.

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The control unit generates the timing and control signals needed to execute instructions; it can be hardwired (fixed logic circuits — fast but hard to modify) or microprogrammed (control signals generated by microinstructions stored in control memory — flexible and easy to modify).

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Control memory is a ROM that stores the microprogram; the Control Address Register (CAR) holds the address of the next microinstruction, while the Control Data Register (CDR) (or pipeline register) holds the current microinstruction being executed.

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Addressing/sequencing logic determines the next microinstruction address — sequential, or a branch/conditional branch based on status bits.

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A microinstruction format may be horizontal (one bit per control signal — wide, but no decoding needed, fast) or vertical (encoded fields need a decoder — narrow, but slower).

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Instruction formats: zero-address (operands taken implicitly from a stack), one-address (one explicit operand, the other implied — usually the accumulator), two-address (two explicit operands, result usually overwrites one), three-address (two source operands plus a separate destination operand).

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Addressing modes: immediate (operand value given directly in the instruction), direct (instruction gives the memory address holding the operand), indirect (instruction gives an address that holds the address of the operand).

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Addressing modes continued: register (operand held in a CPU register), register indirect (a register holds the address of the operand in memory), indexed/base register (effective address = base/index register value + offset), relative (effective address = program counter (PC) value + offset).

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RISC uses a small, simple, fixed-length instruction set with mostly single-cycle execution, few addressing modes, and a load/store architecture relying on more registers and compiler optimization.

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CISC uses a large set of complex, variable-length instructions that may take multiple cycles, supports many addressing modes including memory-to-memory operations, has fewer registers, and does more work in hardware/microcode.

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Pipelining overlaps the execution stages (fetch, decode, execute, memory access, write-back) of successive instructions to increase instruction throughput, without reducing the time for a single instruction.

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Pipeline hazards: structural (hardware resource conflict), data (an instruction depends on the result of a previous, not-yet-completed instruction), and control (caused by branch instructions changing the instruction flow).

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Addition/subtraction in computers is usually performed using 2's complement representation, which allows subtraction to be done as addition of the negated number.

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Multiplication can be performed by repeated addition and shifting; Booth's algorithm speeds this up by handling strings of 1s and 0s efficiently, working correctly for both signed and unsigned numbers.

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Division is performed by repeated subtraction and shifting, using restoring or non-restoring division algorithms.

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Logical operations (AND, OR, XOR, NOT) and shift operations (logical shift, arithmetic shift, rotate) are performed by the ALU on binary data.

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The memory hierarchy arranges storage by speed, cost, and capacity: CPU registers (fastest, smallest, most expensive) → cache memory → main memory (RAM) → secondary storage (disk, SSD — slowest, largest, cheapest).

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Internal memory refers to semiconductor memory directly addressable by the CPU (RAM, ROM, cache); external memory refers to secondary storage devices (hard disk, magnetic tape, optical disks).

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Cache memory works on the principle of locality of reference: temporal locality (recently used data is likely to be used again soon) and spatial locality (data near recently used data is likely to be used soon).

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Cache size: larger caches improve hit rate but increase cost and access time.

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Mapping function: direct mapping (each block maps to exactly one cache line), fully associative (a block can go anywhere), set-associative (a compromise — a block maps to a specific set of lines).

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Replacement algorithm: LRU (Least Recently Used), FIFO (First-In-First-Out), LFU (Least Frequently Used), Random — used when a new block must replace an existing one, needed for associative/set-associative mapping.

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Write policy: write-through (writes go to cache and main memory simultaneously — simple, more traffic) vs write-back (writes go to cache only; main memory updated later when the block is replaced — less traffic, more complex).

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Modern systems commonly use multiple cache levels: L1 (fastest, smallest, per-core), L2, and L3 (larger, shared, slower).

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RAM (Random Access Memory) is volatile and both readable and writable; it loses data on power loss. ROM (Read-Only Memory) is non-volatile and normally only readable after manufacture.

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PROM (Programmable ROM) can be written once by the user; EPROM is erased using UV light then reprogrammed; EEPROM/Flash are electrically erasable and reprogrammable, non-volatile.

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Peripheral devices include input devices (keyboard, mouse), output devices (monitor, printer), and storage devices (disk drives).

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An I/O module (interface) connects peripherals to the system bus, handling control & timing, and communicating with both the CPU and the device.

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I/O module functions also include data buffering and error detection.

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Programmed I/O: the CPU continuously polls the device status (busy-waiting) and transfers data itself — simple but wastes CPU time.

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Interrupt-driven I/O: the device interrupts the CPU when it is ready, so the CPU can perform other work while waiting — more efficient than polling.

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Direct Memory Access (DMA): a dedicated DMA controller transfers data directly between the device and main memory without CPU involvement in the actual transfer.

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The CPU only initiates a DMA transfer and is notified on completion — DMA is fastest for bulk transfers.

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A multiprocessor system has two or more CPUs that can execute instructions simultaneously, increasing overall system performance.

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Tightly coupled multiprocessors share a common main memory (shared-memory systems).

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Loosely coupled multiprocessors have their own local memory and communicate via message passing (distributed systems).

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Interconnection structures link processors, memory, and I/O: common bus, crossbar switch, multistage interconnection network, and hypercube topologies — each trades off cost against bandwidth/scalability.

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Inter-processor synchronization in tightly coupled systems uses shared memory with primitives (semaphores, locks/mutexes); loosely coupled systems use message passing.

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An embedded system is a combination of hardware and software designed to perform a specific, dedicated function within a larger system (e.g., a washing machine controller, an automotive ECU).

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Classification by scale/complexity: small-scale (single 8/16-bit microcontroller), medium-scale, and large-scale (32/64-bit processors, complex OS) embedded systems.

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Classification by functional requirement: hard real-time (missing a deadline is a failure), soft real-time (occasional missed deadlines are tolerable), standalone systems, networked/communication systems, and mobile embedded systems.

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General-Purpose Processor (GPP): programmable for any task; flexible but less efficient for one specific function.

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Single-Purpose Processor: custom-designed hardware (e.g., an ASIC) that executes exactly one function — fast, low power, but inflexible and costly to change.

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Application-Specific Instruction-set Processor (ASIP): a processor with an instruction set customized/optimized for a particular application domain (e.g., DSPs, network processors) — a middle ground between GPP and single-purpose.

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A custom single-purpose processor is built from a datapath (registers, ALU, muxes — performs the actual operations) controlled by a controller (a finite state machine, FSM, that sequences the datapath operations).

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Design flow: capture the desired behavior → translate it into a datapath + FSM controller → optimize the design.

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Optimizing a custom processor targets area, performance, and power — e.g., by sharing hardware resources, reducing the number of states/cycles, or minimizing switching activity.

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Basic architecture/operation: for a programmable processor, operation follows the classic fetch – decode – execute cycle, viewed by the programmer through its instruction set (the "programmer's view").

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A typical embedded development environment includes a cross-compiler, assembler, linker, debugger, and simulator, since code is developed on one machine (host) and runs on another (target).

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A process is an independent program in execution with its own memory space; a thread is a lightweight unit of execution within a process, sharing the process's memory with other threads.

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Multiprocessing means multiple CPUs execute processes simultaneously; multitasking means multiple tasks/processes appear to run concurrently on a single (or few) CPU(s) through fast time-sharing.

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A task in an RTOS is a schedulable unit of work, similar to a process/thread, that the scheduler assigns CPU time to.

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FCFS (First-Come-First-Served): tasks are executed in the order they arrive; simple but can cause long waits.

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Round Robin: each task gets a fixed time slice (quantum) in rotation; fair, good for time-sharing.

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Priority-based scheduling: higher-priority tasks are executed before lower-priority ones.

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Rate Monotonic Scheduling (RMS): a fixed-priority algorithm for periodic tasks — shorter period gets higher priority; common in hard real-time systems.

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Earliest Deadline First (EDF): a dynamic-priority algorithm — the task with the nearest deadline runs first; optimal for uniprocessor scheduling.

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Task synchronization mechanisms — semaphores, mutexes, message passing — coordinate access to shared resources and prevent race conditions between concurrent tasks.

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A device driver is a software module that provides a standard interface allowing the operating system and applications to communicate with hardware peripherals.

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Open-loop control: output is not measured or fed back; no correction for disturbances/errors; simple and cheaper (e.g., a basic toaster timer).

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Closed-loop (feedback) control: output is measured and fed back for comparison; automatically corrects for disturbances/errors; more complex and accurate (e.g., a thermostat-controlled heater).

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VHDL (VHSIC Hardware Description Language) is a language used to describe the structure and behavior of digital circuits, for both simulation and synthesis into actual hardware.

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A VHDL design has two main parts: the entity (declares the circuit's input/output interface — the "black box" ports) and the architecture (describes the internal behavior or structure).

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Modeling styles: behavioral (describes what the circuit does, using processes), structural/dataflow (describes the circuit as interconnected components/signal assignments), and mixed (a combination of both).

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Common VHDL data types include bit, bit_vector, std_logic, std_logic_vector, integer, and boolean.

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VHDL can represent both signed and unsigned binary data; arithmetic operations on signed data must check for overflow when the result exceeds the representable range.

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Combinational logic in VHDL is described using concurrent signal assignment statements or a process with a sensitivity list that reacts to any input change (no clock involved).

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Sequential logic in VHDL is described using a process with a clock signal in its sensitivity list, typically using a construct like if rising_edge(clk) then ... so outputs change only at clock edges.

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Pipelining in VHDL is implemented by inserting clocked registers between combinational logic stages, so each stage's result is latched before feeding the next stage — increasing throughput just like hardware pipelining.

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Integration levels: SSI (tens of transistors/gates, e.g., basic logic gates), MSI (hundreds, e.g., counters, multiplexers), LSI (thousands, e.g., simple processors, memory chips).

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Integration levels continued: VLSI (hundreds of thousands to millions of transistors, e.g., modern microprocessors), ULSI (tens of millions+ transistors on a single chip).

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CMOS (Complementary Metal-Oxide-Semiconductor) is the dominant fabrication technology for modern digital ICs due to its very low static power consumption.