Computer Organization and Embedded System

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This section covers control unit design (hardwired and microprogrammed), CPU structure and instruction formats, addressing modes, data transfer/manipulation instructions, the RISC vs CISC design philosophies, and pipelining.

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Control Unit Design Approach Description Hardwired control Control signals generated by fixed combinational logic circuits; fast but difficult to modify/extend Microprogrammed control Control signals generated by a sequence of microinstructions stored in control memory (control store); each machine instruction maps to a routine in this control memory; flexible/easily modified but somewhat slower Control memory / microinstruction format Control memory stores microinstructions, each encoding the control signals for one micro-operation; address sequencing determines the next microinstruction to fetch (sequential, branch, or subroutine-based) CPU Structure & Function A CPU comprises the ALU (arithmetic/logic operations), registers (fast local storage), and the control unit (sequencing/coordination), interconnected by internal buses.

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Instruction format specifies the layout of an instruction: opcode (operation) field and one or more operand/address fields.

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Addressing modes (immediate, direct, indirect, register, indexed, relative) determine how the effective operand address is computed from the instruction's address field(s).

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Data transfer and manipulation instructions: data transfer (load, store, move), arithmetic (add, subtract), logical (AND, OR, shift), and program control (branch, jump, call) instruction classes.

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RISC vs CISC Aspect RISC CISC Instruction set Small, simple, fixed-length instructions Large, complex, variable-length instructions Execution Mostly single-cycle execution, register-based operations Multi-cycle execution, direct memory operands allowed Control unit Typically hardwired (fast) Typically microprogrammed (flexible) Compiler complexity More complex compiler (more instructions needed per task) Simpler compiler (each instruction does more work) Pipelining & Parallel Processing Pipelining overlaps execution of multiple instructions across stages (e.g. fetch, decode, execute, memory access, write-back), increasing instruction throughput without reducing individual instruction latency.

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Pipeline hazards (structural, data, control) can stall the pipeline; techniques like forwarding, branch prediction, and stalling mitigate them.

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Parallel processing executes multiple instructions/tasks simultaneously using multiple functional units or processors, going beyond what pipelining alone achieves.

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This section covers computer arithmetic/logical operations, the memory hierarchy, internal vs external memory, cache memory principles, and the key elements of cache design that determine its performance.

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Arithmetic & Logical Operations The ALU performs arithmetic operations (add, subtract, multiply, divide — typically using 2's complement representation) and logical operations (AND, OR, XOR, NOT, shift/rotate) on binary operands.

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The Memory Hierarchy Level Characteristic Registers Fastest, smallest, most expensive per bit; inside the CPU Cache memory Very fast; bridges the speed gap between CPU and main memory Main memory (internal) RAM; moderate speed; directly addressable by the CPU Secondary/external memory Hard disk, SSD; slow, large capacity, non-volatile, cheapest per bit The hierarchy exploits the principle of locality of reference (temporal and spatial) — recently/nearby- accessed data is likely to be accessed again soon, justifying caching.

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Cache Memory Principles & Design Elements Design Element Options / Description Cache size Larger cache generally improves hit rate but increases cost and access time Mapping function Direct mapping (each block maps to exactly one cache line), fully associative (any block can go in any line), set-associative (compromise: block maps to a specific set, any line within it) Replacement algorithm Determines which block to evict when the cache is full:

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LRU (Least Recently Used), FIFO, random, etc.

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(relevant for associative/set-associative caches) Write policy Write-through (updates cache and main memory simultaneously, simpler, more traffic) vs write- back (updates cache only, writes to memory on eviction, faster, more complex) Number of caches Split (separate instruction/data) vs unified cache; single-level vs multi-level (L1/L2/L3) cache hierarchies Memory write ability & storage permanence:

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RAM (read-write, volatile) vs ROM (read-only or limited- write, non-volatile) — the two axes used to classify memory devices.

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Composing memory: larger memory modules can be built by combining smaller chips, increasing either word size (chips in parallel) or address space (chips selected by address decoding).

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This section covers peripheral devices and I/O modules, the various data transfer modes including DMA, and the characteristics, interconnection structures, and communication/synchronization mechanisms of multiprocessor systems.

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Peripheral Devices & I/O Modules Peripheral devices (keyboard, display, disk, printer) connect to the computer through I/O modules, which handle the electrical/timing mismatch between fast CPU/memory and typically slower peripherals.

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An I/O interface provides address decoding, data buffering/registers, and status/control signaling between the CPU and the peripheral.

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Modes of Data Transfer Mode Description Programmed I/O CPU actively polls the device status and transfers each data item itself; simple but wastes CPU time waiting Interrupt-driven I/O Device signals the CPU (via interrupt) only when ready, letting the CPU perform other work in between; more efficient than polling Direct Memory Access (DMA) A DMA controller transfers data directly between the device and memory without CPU involvement per byte, freeing the CPU almost entirely during bulk transfers Multiprocessor Systems A multiprocessor system contains multiple CPUs sharing memory and I/O resources, enabling true parallel execution of tasks.

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Interconnection structures: common bus (simple, shared, can become a bottleneck), crossbar switch (any-to-any connectivity, expensive), multistage/hierarchical networks (scalable compromise).

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Inter-processor communication: processors exchange data typically via shared memory (common address space) or message passing (explicit send/receive over the interconnect).

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Synchronization: mechanisms like semaphores, locks, and barriers coordinate access to shared resources and ensure correct ordering of operations across processors, preventing race conditions.

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This section covers the overview and classification of embedded systems, custom single-purpose processor design and optimization, general-purpose vs application-specific processors, and embedded system development environments.

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Embedded Systems Overview & Classification An embedded system is a combination of hardware and software designed to perform one or a few dedicated functions, typically as part of a larger device, unlike a general-purpose computer.

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Embedded systems are often classified by performance/time requirements (real-time vs non-real-time; hard vs soft real-time), and by processing architecture (single-purpose, general-purpose, application- specific).

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Processor Types for Embedded Systems Processor Type Description General-purpose processor Standard programmable microprocessor executing software; flexible, reusable across applications, but not optimized for any one task Custom single-purpose processor (ASIC-based) Digital circuit designed to execute exactly one specific program/function; fastest, most power/area-efficient, but inflexible and costly to design/change Application-Specific Instruction-Set Processor (ASIP) A processor with an instruction set customized/optimized for a particular application domain (e.g.

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DSP), balancing flexibility and efficiency between general-purpose and single-purpose extremes Custom Single-Purpose Processor Design Basic architecture: a datapath (registers, ALU, connections tailored to the specific algorithm) controlled by a finite-state-machine-based controller (analogous to a control unit) — no general-purpose instruction fetch/decode overhead.

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Optimizing custom processors: techniques include pipelining the datapath, parallelizing operations, and eliminating unused functional units to reduce area, power, and increase speed for the specific target function.

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Operation and programmer's view: since the design directly implements the algorithm in hardware, there is no traditional 'programming' in the general-purpose sense — behavior is fixed by the hardware structure itself.

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Development Environment Embedded system development typically uses cross-compilers/cross-assemblers (compiling on a host machine for a different target architecture), simulators/emulators, and in-circuit debuggers/JTAG interfaces for testing on real hardware.

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This section covers operating system fundamentals (tasks, processes, threads), multitasking/multiprocessing, task scheduling and synchronization, device drivers, and an overview of open-loop and closed-loop control systems.

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OS Basics — Tasks, Processes & Threads Concept Description Process An independent program in execution, with its own separate memory address space Thread A lightweight unit of execution within a process, sharing the process's memory/resources with other threads of the same process Task A general term (especially in RTOS contexts) for a unit of work to be scheduled and executed, often implemented as a thread or process Multiprocessing, Multitasking & Scheduling Multitasking: a single processor appears to run multiple tasks concurrently by rapidly switching between them (time-slicing).

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Multiprocessing: multiple processors execute tasks truly simultaneously, in parallel.

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Task scheduling algorithms decide which ready task runs next: e.g.

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Round-Robin (time-sliced, fair), Priority-based (highest priority runs first), Rate-Monotonic (fixed priority by period, common in hard real-time systems), Earliest-Deadline-First (dynamic priority by deadline).

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Synchronization & Device Drivers Task synchronization mechanisms (semaphores, mutexes, message queues, event flags) coordinate access to shared resources and communication between concurrent tasks, avoiding race conditions and deadlock.

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A device driver is software providing a standard interface between the operating system/application and a specific hardware peripheral, hiding hardware-specific details.

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Control Systems Overview Control Type Description Open-loop control system Output is not fed back to influence the input/control action; simple, but cannot automatically correct for disturbances or errors Closed-loop (feedback) control system Output is measured and fed back, compared with the desired reference, and the error used to adjust the control action — can automatically compensate for disturbances

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This final section of the chapter introduces VHDL as a hardware description language, data representation and overflow handling, and the use of VHDL to design combinational, sequential, and pipelined digital logic.

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VHDL Overview VHDL (VHSIC Hardware Description Language) is a language used to describe the structure and behavior of digital electronic systems, enabling simulation and synthesis into actual hardware (FPGA/ASIC).

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A VHDL design typically consists of an entity (defines the interface: input/output ports) and an architecture (defines the internal behavior/structure implementing that interface).

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VHDL supports multiple description styles: behavioral (describes what the circuit does, algorithmically), dataflow (describes signal flow via concurrent assignments), and structural (describes the circuit as an interconnection of components).

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Data Representation & Overflow VHDL provides data types for representing bits and numbers (bit, std_logic, integer, signed/unsigned vectors) used to model hardware signals of arbitrary width.

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Overflow occurs in arithmetic operations when the result exceeds the representable range of the chosen bit width;

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VHDL designs must explicitly handle/detect overflow (e.g. by widening the result or checking carry/sign bits) since hardware does not automatically resize.

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Designing Logic with VHDL Logic Type VHDL Modeling Approach Combinational logic Modeled using concurrent signal assignments or a process with a sensitivity list covering all inputs (no clock/memory element) Sequential logic Modeled using a process sensitive to a clock edge (e.g. rising_edge(clk)), with signals assigned inside to represent flip-flop/register behavior Pipelining in VHDL Implemented by inserting register stages (clocked processes) between combinational blocks, so each stage's output is latched before feeding the next stage, increasing throughput just as in hardware pipelining generally