ACtE/Chapter 2/Read MCQs
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Chapter 2 Β· MCQ Read Mode

Digital Logic and Microprocessor

AEXE02Β·88 Total MCQs
Question 1 of 88Digital Logic

The binary equivalent of decimal 13 is:

A1101
B1011
C1110
D1001
Answer is hidden
Question 2 of 88Digital Logic

The base (radix) of the hexadecimal number system is:

A8
B10
C16
D2
Answer is hidden
Question 3 of 88Digital Logic

Which gate is known as a β€œuniversal gate”?

AAND
BOR
CNAND
DXOR
Answer is hidden
Question 4 of 88Digital Logic

The output of an XOR gate is HIGH when:

ABoth inputs are the same
BBoth inputs are different
CBoth inputs are LOW
DBoth inputs are HIGH
Answer is hidden
Question 5 of 88Digital Logic

De Morgan’s theorem states that (A+B)’ equals:

AA’+B’
BA’·B’
CAΒ·B
DA+B
Answer is hidden
Question 6 of 88Digital Logic

SOP stands for:

ASum of Products
BSeries of Parallels
CSet of Points
DSequence of Pulses
Answer is hidden
Question 7 of 88Digital Logic

A Karnaugh map (K-map) is primarily used to:

AIncrease propagation delay
BSimplify Boolean expressions
CConvert AC to DC
DStore binary data
Answer is hidden
Question 8 of 88Digital Logic

A standard Karnaugh map used for simplifying expressions of 4 variables has how many cells?

A4
B8
C16
D32
Answer is hidden
Question 9 of 88Digital Logic

In a POS expression, individual sum terms are combined by:

AMultiplication (AND) of sums
BAddition (OR) of products
CXOR operation
DSubtraction
Answer is hidden
Question 10 of 88Digital Logic

NAND and NOR gates are called universal gates because:

AThey consume the least power
BAny logic function can be implemented using only NAND or only NOR gates
CThey are the fastest gates available
DThey require no truth table
Answer is hidden
Question 11 of 88Combinational & Arithmetic Circuits

A multiplexer with 4 select lines can select among how many inputs?

A4
B8
C16
D2
Answer is hidden
Question 12 of 88Combinational & Arithmetic Circuits

A demultiplexer performs the opposite function of a:

ADecoder
BMultiplexer
CEncoder
DAdder
Answer is hidden
Question 13 of 88Combinational & Arithmetic Circuits

A decoder with n input lines can produce up to how many output lines?

An
B2n
C2ⁿ
DnΒ²
Answer is hidden
Question 14 of 88Combinational & Arithmetic Circuits

A priority encoder resolves the situation when:

AAll inputs are LOW
BMultiple inputs are active simultaneously
CThe clock signal fails
DThe output is undefined
Answer is hidden
Question 15 of 88Combinational & Arithmetic Circuits

A half adder can add:

ATwo bits, producing sum and carry
BThree bits including a carry-in
COnly a single bit with no carry
DMultiple full bytes
Answer is hidden
Question 16 of 88Combinational & Arithmetic Circuits

A full adder differs from a half adder because it additionally accepts a:

AClock input
BCarry-in input
CReset input
DSelect input
Answer is hidden
Question 17 of 88Combinational & Arithmetic Circuits

In 2’s complement arithmetic, subtraction is performed by:

ADirect binary subtraction only
BAdding the 2’s complement of the subtrahend
CUsing a completely separate subtractor circuit
DDividing by 2
Answer is hidden
Question 18 of 88Combinational & Arithmetic Circuits

The range of an 8-bit signed number in 2’s complement form is:

A0 to 255
Bβˆ’128 to +127
Cβˆ’127 to +127
Dβˆ’255 to +255
Answer is hidden
Question 19 of 88Combinational & Arithmetic Circuits

In sign-magnitude representation, the MSB represents:

AThe value
BThe sign
CThe carry
DThe parity
Answer is hidden
Question 20 of 88Combinational & Arithmetic Circuits

The 1’s complement of the binary number 1010 is:

A0101
B1011
C0110
D1010
Answer is hidden
Question 21 of 88Sequential Logic Circuits

An SR flip-flop has an invalid (undefined) state when:

AS=0, R=0
BS=1, R=1
CS=1, R=0
DS=0, R=1
Answer is hidden
Question 22 of 88Sequential Logic Circuits

A gated (clocked) flip-flop responds to its inputs:

AOnly during the active clock level
BOnly at the clock edge
CContinuously regardless of clock
DNever
Answer is hidden
Question 23 of 88Sequential Logic Circuits

An edge-triggered flip-flop changes state:

ADuring the entire clock pulse
BOnly at the rising or falling edge of the clock
CWhen power is first applied
DRandomly
Answer is hidden
Question 24 of 88Sequential Logic Circuits

The master-slave flip-flop configuration is primarily used to:

AIncrease power consumption
BEliminate the race-around condition in JK flip-flops
CReduce the number of gates needed
DAdd a reset input
Answer is hidden
Question 25 of 88Sequential Logic Circuits

A shift register that accepts data serially and outputs it in parallel is called:

ASISO
BSIPO
CPISO
DPIPO
Answer is hidden
Question 26 of 88Sequential Logic Circuits

In an asynchronous (ripple) counter, the flip-flops are triggered by:

AA common clock signal simultaneously
BThe output of the preceding flip-flop
CAn external reset only
DRandom pulses
Answer is hidden
Question 27 of 88Sequential Logic Circuits

Compared to asynchronous counters, synchronous counters are:

ASlower, due to cumulative delay
BFaster, since all flip-flops switch together
CUnable to count upward
DOnly usable for down-counting
Answer is hidden
Question 28 of 88Sequential Logic Circuits

A JK flip-flop with J=K=1 at the active clock edge will:

AReset
BSet
CToggle its output
DRemain unchanged
Answer is hidden
Question 29 of 88Sequential Logic Circuits

A D flip-flop transfers its D input to the output:

AContinuously
BAt the active clock edge
CNever
DOnly when reset
Answer is hidden
Question 30 of 88Sequential Logic Circuits

Ring counters and Johnson counters are typical applications built from:

ADecoders
BShift registers
CMultiplexers
DAdders
Answer is hidden
Question 31 of 88Microprocessor Architecture & Assembly Programming

The part of a microprocessor that performs arithmetic and logic operations is the:

AControl unit
BALU
CProgram counter
DStack pointer
Answer is hidden
Question 32 of 88Microprocessor Architecture & Assembly Programming

The register that holds the address of the next instruction to be executed is the:

AAccumulator
BProgram Counter (PC)
CStack Pointer
DInstruction Register
Answer is hidden
Question 33 of 88Microprocessor Architecture & Assembly Programming

In assembly language, a mnemonic represents:

AA memory address
BA symbolic name for a machine instruction
CA data value only
DA hardware pin
Answer is hidden
Question 34 of 88Microprocessor Architecture & Assembly Programming

The three main buses in a microprocessor system are:

AData, Address, Control
BSerial, Parallel, USB
CInput, Output, Memory
DClock, Reset, Power
Answer is hidden
Question 35 of 88Microprocessor Architecture & Assembly Programming

A program that converts assembly language into machine code is called a(n):

ACompiler
BAssembler
CInterpreter
DLinker
Answer is hidden
Question 36 of 88Microprocessor Architecture & Assembly Programming

The accumulator in a microprocessor is primarily used to:

AStore the next instruction’s address
BHold operands and results of ALU operations
CControl the clock frequency
DStore the stack base address
Answer is hidden
Question 37 of 88Microprocessor Architecture & Assembly Programming

The address bus in a microprocessor is:

ABidirectional, carries data
BUnidirectional, carries memory/IO addresses
CUsed only for control signals
DNot connected to memory
Answer is hidden
Question 38 of 88Microprocessor Architecture & Assembly Programming

Branch (jump) instructions in assembly language are used to:

APerform arithmetic operations only
BAlter the normal sequential flow of program execution
CTransfer data between registers only
DPermanently halt the processor
Answer is hidden
Question 39 of 88Microprocessor Architecture & Assembly Programming

The word length of a microprocessor refers to:

AThe number of instructions it executes per second
BThe number of bits it can process/transfer at once
CThe size of its cache memory
DThe number of registers only
Answer is hidden
Question 40 of 88Microprocessor Architecture & Assembly Programming

Data transfer instructions in assembly language typically move data between:

ARegisters and/or memory
BOnly two ALUs
CPower supply rails
DClock sources
Answer is hidden
Question 41 of 88Interfacing (Microprocessor System)

RAM stands for:

ARead Access Memory
BRandom Access Memory
CRapid Address Memory
DRead-Ahead Memory
Answer is hidden
Question 42 of 88Interfacing (Microprocessor System)

Which memory type retains its content even when power is switched off?

ASRAM
BDRAM
CROM
DCache
Answer is hidden
Question 43 of 88Interfacing (Microprocessor System)

In memory-mapped I/O, peripheral devices are:

AAccessed only with dedicated I/O instructions
BTreated as if they occupy part of the memory address space
CNever addressable by the CPU
DConnected directly to the ALU
Answer is hidden
Question 44 of 88Interfacing (Microprocessor System)

The PPI (Programmable Peripheral Interface) is primarily used for:

ASerial communication only
BParallel I/O interfacing
CAnalog signal conversion
DClock generation
Answer is hidden
Question 45 of 88Interfacing (Microprocessor System)

In asynchronous serial transmission, each data character is framed with:

AA parity bit only
BStart and stop bits
CA checksum only
DNo framing bits
Answer is hidden
Question 46 of 88Interfacing (Microprocessor System)

RS232 is a standard primarily used for:

AParallel data transmission
BSerial data communication
CPower distribution
DVideo signals
Answer is hidden
Question 47 of 88Interfacing (Microprocessor System)

USART stands for:

AUniversal Synchronous/Asynchronous Receiver Transmitter
BUnified Serial Address Register Transfer
CUniversal System Address Read Transfer
DUniform Synchronous Analog Receiver Transmitter
Answer is hidden
Question 48 of 88Interfacing (Microprocessor System)

DMA (Direct Memory Access) allows data transfer between memory and I/O:

AOnly through continuous CPU intervention
BWithout direct CPU intervention for each data word
COnly during interrupts
DOnly in serial form
Answer is hidden
Question 49 of 88Interfacing (Microprocessor System)

Compared to RS232, USB offers:

ALower data rates and no plug-and-play
BHigher data rates and plug-and-play capability
COnly power transfer, no data
DParallel transmission only
Answer is hidden
Question 50 of 88Interfacing (Microprocessor System)

In synchronous serial transmission, timing is coordinated by:

AStart/stop bits on every character
BA shared clock signal
CRandom polling
DFixed delays only
Answer is hidden
Question 51 of 88Interrupt Operations

An interrupt is best described as:

AA permanent halt of the processor
BA signal that temporarily suspends normal execution to service an event
CA type of memory device
DA logic gate
Answer is hidden
Question 52 of 88Interrupt Operations

A hardware interrupt is typically triggered by:

AA program instruction executed deliberately
BAn external device requiring attention
CThe compiler
DThe interrupt vector table itself
Answer is hidden
Question 53 of 88Interrupt Operations

A non-maskable interrupt (NMI) is characterized by:

ABeing easily disabled by software
BBeing reserved for critical events and unable to be disabled
CNever being serviced
DRequiring polling instead of a signal
Answer is hidden
Question 54 of 88Interrupt Operations

An Interrupt Service Routine (ISR) is:

AThe main program itself
BA subroutine executed in response to a specific interrupt
CA type of memory chip
DA logic gate used for gating clocks
Answer is hidden
Question 55 of 88Interrupt Operations

The interrupt vector table is used to:

AStore user data files
BStore the starting addresses of ISRs, indexed by interrupt type
CPerform arithmetic operations
DGenerate the system clock
Answer is hidden
Question 56 of 88Interrupt Operations

When an interrupt occurs, before jumping to the ISR, the processor must first:

AErase all memory
BComplete the current instruction and save its context (state)
CImmediately power off
DIgnore the interrupt permanently
Answer is hidden
Question 57 of 88Interrupt Operations

At the end of an ISR, a return-from-interrupt instruction is used to:

APermanently halt the processor
BRestore saved context and resume the original program
CTrigger another interrupt
DErase the interrupt vector table
Answer is hidden
Question 58 of 88Interrupt Operations

Compared to polling, using interrupts is generally more efficient because:

AThe CPU must constantly check device status
BThe CPU can perform other work until an event actually occurs
CInterrupts require no processing at all
DPolling is always faster
Answer is hidden
Question 59 of 88Interrupt Operations

A software interrupt is typically triggered by:

AAn external hardware device only
BAn instruction deliberately executed within a program
CA power failure
DA clock signal alone
Answer is hidden
Question 60 of 88Interrupt Operations

Interrupt priority schemes are needed primarily to:

APrevent any interrupts from ever occurring
BDetermine which interrupt is serviced first when multiple occur simultaneously
CIncrease memory capacity
DEliminate the need for an ISR
Answer is hidden
Question 61 of 88Computer Organization

The unit responsible for generating control signals to coordinate CPU operations is the:

AALU
BControl Unit
CCache memory
DData bus
Answer is hidden
Question 62 of 88Computer Organization

In a microprogrammed control unit, control signals are generated from:

AA hardwired logic circuit only
BA control memory storing microinstructions
CAn external keyboard
DA random number generator
Answer is hidden
Question 63 of 88Computer Organization

An instruction format typically consists of:

AOnly an opcode
BAn opcode and operand(s)/address field(s)
COnly a memory address
DOnly a clock signal
Answer is hidden
Question 64 of 88Computer Organization

The addressing mode in which the operand value is given directly in the instruction is called:

ADirect addressing
BImmediate addressing
CIndirect addressing
DIndexed addressing
Answer is hidden
Question 65 of 88Computer Organization

In indirect addressing, the instruction specifies:

AThe operand itself
BThe address of a memory location that holds the operand’s address
CA register holding the operand directly
DNothing at all
Answer is hidden
Question 66 of 88Computer Organization

RISC architecture is characterized by:

AA large, complex instruction set
BA small, simple, uniform-length instruction set optimized for pipelining
CThe complete absence of registers
DOnly microprogrammed control
Answer is hidden
Question 67 of 88Computer Organization

CISC architecture is characterized by:

AA small number of simple instructions
BA large set of complex, variable-length instructions
CNo addressing modes at all
DExclusively single-cycle instructions
Answer is hidden
Question 68 of 88Computer Organization

Pipelining in a CPU improves performance mainly by:

AExecuting multiple instruction stages concurrently
BIncreasing the clock period
CRemoving the need for registers
DReducing the instruction set to one instruction
Answer is hidden
Question 69 of 88Computer Organization

A pipeline hazard that occurs when an instruction depends on the result of a previous, unfinished instruction is called a:

AStructural hazard
BData hazard
CControl hazard
DMemory hazard
Answer is hidden
Question 70 of 88Computer Organization

The arithmetic and logic unit (ALU) primarily performs:

AInstruction fetching only
BArithmetic and logical operations on data
CAddress decoding only
DClock generation
Answer is hidden
Question 71 of 88Digital Electronics

How many NOT gates are required to build a 2:1 Multiplexer?

A1
B2
C3
D4
Answer is hidden
Question 72 of 88Digital Electronics

How many 2-input NAND gates are contained in a standard 7400 TTL IC?

A2
B3
C4
D8
Answer is hidden
Question 73 of 88Digital Electronics

In TTL logic, what is the input voltage range for a logic LOW (active LOW level)?

A0 V to 0.8 V
B0 V to 1.5 V
C2 V to 5 V
D0.8 V to 2 V
Answer is hidden
Question 74 of 88Digital Electronics

When an invalid BCD code (1010–1111) is detected and auto-corrected, what value is added?

A0110 (6)
B0001 (1)
C1010 (10)
D0100 (4)
Answer is hidden
Question 75 of 88Digital Electronics

What is the terminal (reset) state of a MOD-10 (decade) counter?

A1010
B1001
C1000
D0111
Answer is hidden
Question 76 of 88Digital Electronics

What is the minimum number of flip-flops (memory blocks) required to build a MOD-6 ripple counter?

A2
B3
C4
D6
Answer is hidden
Question 77 of 88Digital Electronics

An SR flip-flop is also called a:

AMonostable multivibrator
BBistable multivibrator
CAstable multivibrator
DSchmitt trigger
Answer is hidden
Question 78 of 88Digital Electronics

A JK flip-flop with J = 1 and K = 1 is clocked at 20 kHz. What is the output waveform and its frequency?

ASine wave at 20 kHz
BSquare wave at 20 kHz
CSine wave at 10 kHz
DSquare wave at 10 kHz
Answer is hidden
Question 79 of 88Digital Electronics

What is the duty cycle of an ideal astable multivibrator?

A25%
B50%
C75%
D100%
Answer is hidden
Question 80 of 88Digital Electronics

Which of the following is NOT a valid operation of flip-flops?

ASet
BReset
CToggle
DMultiply
Answer is hidden
Question 81 of 88Digital Electronics

The TRAP interrupt in 8085 microprocessor is:

AEdge-triggered only
BLevel-triggered (high level)
CMaskable
DSoftware interrupt
Answer is hidden
Question 82 of 88Digital Electronics

Small-Scale Integration (SSI) refers to ICs with how many transistors?

ALess than 10
B10–99
C100–999
D1000+
Answer is hidden
Question 83 of 88Digital Electronics

In VHDL, a signal that represents a bus (multi-bit connection) is declared as:

AVariable
BSignal
CConstant
DGeneric
Answer is hidden
Question 84 of 88Digital Electronics

In VHDL, the primary design unit that represents a hardware block's interface (ports and generics) is called:

AArchitecture
BPackage
CComponent
DEntity
Answer is hidden
Question 85 of 88Digital Electronics

The shadow mask technique is used in:

ALCD panels
BCRT displays
COLED displays
DPlasma screens
Answer is hidden
Question 86 of 88Digital Electronics

Left-shifting an unsigned binary number by 1 bit is equivalent to:

ADividing by 2
BMultiplying by 2
CAdding 1
DSubtracting 1
Answer is hidden
Question 87 of 88Digital Electronics

The expression x << 3 is equivalent to:

Ax Γ— 8
Bx Γ— 3
Cx + 3
Dx / 8
Answer is hidden
Question 88 of 88Digital Electronics

Which logic gate is commonly used for parity checking and overflow detection?

AAND
BOR
CXOR
DNAND
Answer is hidden
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