Digital Logic and Microprocessor

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Digital circuits work with only two voltage levels: 0 (LOW, ~0 V) and 1 (HIGH, ~5 V or 3.3 V). Everything — video, audio, programs — boils down to these two states.

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Number systems to master: Binary (base 2, digits 0–1), Octal (base 8, digits 0–7), Decimal (base 10), Hexadecimal (base 16, digits 0–9 and A–F).

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Shortcut conversions: 1 hex digit ↔ 4 binary bits exactly. 1 octal digit ↔ 3 binary bits exactly. These groupings make conversions trivial.

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1's complement: flip every bit (0→1, 1→0). 2's complement: flip every bit then add 1. The 2's complement of a number is its negative value in binary — used for subtraction in hardware.

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AND gate: output is 1 ONLY when ALL inputs are 1. Like a series switch — both must close.

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OR gate: output is 1 when ANY input is 1. Like a parallel switch — either one closing works.

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NOT gate: flips the input. NAND = NOT(AND). NOR = NOT(OR).

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NAND and NOR are called universal gates because you can build ANY logic function using only NAND gates, or only NOR gates.

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XOR (exclusive OR): output is 1 when the inputs are DIFFERENT. Key identity: A ⊕ A = 0, A ⊕ 0 = A.

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XNOR: output is 1 when inputs are the SAME — it is the inverse of XOR.

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De Morgan's theorems let you convert AND/OR circuits to NAND/NOR: (A · B)' = A' + B' and (A + B)' = A' · B'.

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Boolean expression forms: SOP (Sum of Products) = OR of AND terms; POS (Product of Sums) = AND of OR terms.

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Karnaugh map (K-map): a grid-based tool that simplifies Boolean expressions visually by grouping adjacent 1s into the largest possible power-of-2 groups. Groups wrap around edges.

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Combinational logic circuits: the output depends ONLY on the current inputs — no memory involved. Same inputs always give the same outputs.

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Multiplexer (MUX): a data selector. It takes 2ⁿ inputs and routes ONE of them to the output, based on n select lines. Think of it as a controlled switch.

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Demultiplexer (DEMUX): the inverse of MUX. One input is directed to ONE of `2ⁿ` outputs. It's a data distributor.

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Encoder: compresses 2ⁿ inputs down to n output bits. Only ONE input is active at a time (e.g., an 8-to-3 priority encoder).

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Decoder: expands n input bits into 2ⁿ outputs. Exactly ONE output is active (HIGH) for each unique input code (e.g., 3-to-8 decoder activates one of 8 lines).

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Half adder: adds two 1-bit numbers A and B. Outputs: Sum = A XOR B, Carry = A AND B. Cannot handle a carry-in from a previous stage.

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Full adder: adds three 1-bit inputs — A, B, and Carry-in (Cin). Outputs: Sum and Carry-out. This is the real building block for multi-bit adders.

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Ripple carry adder: chains full adders together. The carry 'ripples' from LSB to MSB — simple but slow (each stage waits for the previous carry).

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To subtract in binary: instead of building a subtractor, compute A + (2's complement of B). This is how real ALUs subtract.

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Signed binary numbers use 2's complement: the MSB is the sign bit (==0 = positive, 1 = negative==). An n-bit 2's complement represents −2^(n-1) to +(2^(n-1) − 1).

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Sequential circuits have MEMORY — the output depends on both the current inputs AND the past state. They are the foundation of all digital memory and computing.

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The fundamental memory element is the flip-flop — a bistable circuit that holds either 0 or 1 until told to change.

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SR latch/flip-flop: two inputs — S (Set, forces Q=1) and R (Reset, forces Q=0). ==CRITICAL: S=R=1 is the FORBIDDEN state== — gives an unpredictable output.

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D (Data) flip-flop: output Q simply captures input D on the active clock edge. Eliminates the forbidden state — the workhorse of memory and registers.

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JK flip-flop: improves on SR by making both inputs HIGH (J=K=1) cause the output to TOGGLE (Q̄→Q). No forbidden state. Most versatile flip-flop.

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T (Toggle) flip-flop: a simplified JK with both inputs tied together. When T=1, output toggles every clock edge. Natural for counters.

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==Latch = level-triggered== (transparent when clock=1). ==Flip-flop = edge-triggered== (changes only on the rising or falling edge of clock — more predictable).

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Master-slave flip-flop: cascades two latches — the first captures on one clock level, the second outputs on the other. Eliminates the ones catching problem.

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Register: a group of D flip-flops sharing a common clock — stores a multi-bit word. An 8-bit register stores one byte.

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Shift register: data moves one position per clock. SISO, SIPO, PISO, PIPO. Used for serial-to-parallel conversion.

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Asynchronous (ripple) counter: the output of one flip-flop clocks the next. Slow — has cumulative propagation delay. Count ripples from LSB to MSB.

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Synchronous counter: all flip-flops share the SAME clock signal. All change simultaneously — no propagation delay, much faster.

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An n-bit counter has 2ⁿ states, counting from 0 to 2ⁿ − 1 before rolling back to 0.

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A microprocessor is a complete CPU on a single chip — it fetches instructions from memory, decodes them, and executes them. The Intel 8085 is the classic teaching example.

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Three internal blocks: ALU (performs arithmetic and logic), Control Unit (generates timing/control signals, sequences operations), Registers (fast on-chip storage).

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Accumulator (A register): the main working register — most arithmetic and logic results end up here.

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Program Counter (PC): a 16-bit register that ALWAYS points to the memory address of the NEXT instruction to fetch. After each fetch, it automatically increments.

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Stack Pointer (SP): 16-bit register pointing to the TOP of the stack in RAM. The stack is used for CALL/RET and interrupt handling — data is pushed/popped in LIFO order.

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Flag register: a set of 1-bit condition flags set automatically by the ALU. The 8085 flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry (CY).

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The 8085 has a 16-bit address bus → 2¹⁶ = 65,536 addressable locations = 64 KB of memory. The data bus is 8-bit (bidirectional). The address bus is unidirectional (CPU only drives it).

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The lower 8 bits of the address bus are multiplexed with the data bus (AD0–AD7) — the ALE signal distinguishes address from data on these shared lines.

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Assembly language uses human-readable mnemonics (MOV, ADD, JMP, CALL) instead of raw binary opcodes. One mnemonic = one machine instruction.

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An assembler translates assembly source code into machine code (hex object code). A disassembler does the reverse.

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8085 instruction categories: Data Transfer (MOV, MVI, LDA, STA), Arithmetic (ADD, SUB, INR, DCR), Logical (ANA, ORA, XRA, CMA), Branching (JMP, JZ, JC, CALL, RET), Machine Control (HLT, NOP, EI, DI).

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The 8085 fetch-decode-execute cycle: (1) PC → address bus → fetch opcode, (2) decode the opcode, (3) execute the operation, (4) increment PC, repeat.

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Memory is classified as volatile (loses data when power goes off) or non-volatile (retains data). RAM is volatile; ROM and Flash are non-volatile.

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SRAM (Static RAM): each bit is stored in a cross-coupled flip-flop. Fast and needs no refresh, but takes more chip area. Used for CPU cache.

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DRAM (Dynamic RAM): each bit is a tiny capacitor charge. Cheaper and denser than SRAM but must be periodically REFRESHED (the capacitor leaks). Used for main memory.

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ROM types from least to most flexible: ROM (factory-programmed, permanent) → PROM (one-time user-programmable) → EPROM (erasable with UV light) → EEPROM/Flash (electrically erasable, byte/block level).

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Memory hierarchy — trading speed for cost/size (fastest to slowest): CPU Registers → Cache (SRAM) → Main Memory (DRAM) → Secondary Storage (SSD/HDD).

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Parallel interface: multiple data bits transferred simultaneously over multiple wires. Faster over short distances but uses more pins.

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Serial interface: bits transferred one at a time over a single wire. Uses fewer pins — suitable for long distances and external connections.

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PPI 8255 (Programmable Peripheral Interface): an Intel chip providing 3 programmable 8-bit I/O ports (Port A, Port B, Port C) configurable as input or output via software.

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Synchronous serial: sender and receiver share a clock signal — no need for start/stop bits. Examples: SPI, I²C.

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Asynchronous serial: no shared clock. Each data frame is wrapped in a START bit and STOP bit(s) for synchronization. Example: UART (RS-232, RS-485).

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DMA (Direct Memory Access): I/O device reads/writes main memory DIRECTLY, without the CPU in every byte transfer. The CPU hands over the bus (cycle stealing).

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A DMA controller (e.g., Intel 8257) manages the transfer. CPU first programs it with source address, destination address, and byte count, then signals it to proceed.

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An interrupt is a hardware or software signal that tells the CPU: stop what you're doing and handle this urgent event. The CPU finishes its current instruction, then responds.

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Interrupt response sequence: (1) Complete current instruction, (2) Push PC (return address) onto stack, (3) Disable further interrupts, (4) Jump to the ISR (Interrupt Service Routine), (5) After ISR: execute RET/RETI to pop PC and resume.

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Why interrupts? The alternative is POLLING — the CPU wastes time looping and checking device status repeatedly. Interrupts are event-driven: the CPU is notified only when something actually needs attention.

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Hardware interrupt: triggered by an external device asserting an interrupt line (keyboard press, timer overflow, data received). Asynchronous — can happen any time.

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Software interrupt: triggered by a specific instruction in the program (RST 0–7 in 8085). Synchronous — happens at a known point in the code.

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Maskable interrupt: the CPU can DISABLE (mask) it using a software instruction (DI — Disable Interrupts in 8085). While disabled, the CPU ignores these requests.

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Non-Maskable Interrupt (NMI): the CPU CANNOT ignore it — always gets serviced regardless of the interrupt flag. Used for critical events (power failure, memory error).

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Vectored interrupt: the CPU knows exactly where the ISR is (fixed address predefined in hardware or a vector table). Fast response. Example: 8085 RST instructions.

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Non-vectored (polled) interrupt: the CPU must ask the interrupting device 'what do you want?' to determine which ISR to run. Slower but more flexible.

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8085 interrupt priority (highest to lowest): TRAP > RST7.5 > RST6.5 > RST5.5 > INTR. TRAP is the only one that is non-maskable and vectored.

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If multiple interrupts arrive simultaneously, the one with the HIGHEST PRIORITY is serviced first. The others wait.

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ISR design: keep it short and fast. Save registers at entry, restore them before exit. End with RET (or RETI for hardware interrupts).