Digital Electronics, Microprocessors and Signal Processing for BME

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This section covers the basic, derived and universal logic gates, De Morgan's laws, the theorems of Boolean algebra and their use in simplification, and the Karnaugh map for up to four variables.

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Digital Fundamentals • Analogue signals are continuous in amplitude and time; digital signals take only discrete values — in binary logic, two: logic 0 (low) and logic 1 (high).

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Digital systems are preferred because of their noise immunity and signal regeneration, ease of storage and transmission, accuracy set by the number of bits, programmability, reproducibility and the ability to be integrated on a chip; the penalties are quantisation error, bandwidth and the need for conversion at both ends of the chain. • Number systems: binary (base 2), octal (8), decimal (10) and hexadecimal (16), with conversion by repeated division (decimal to binary) and by positional weighting (binary to decimal).

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Binary arithmetic uses 1's and 2's complement for signed numbers, the 2's complement being the 1's complement plus one — the representation used in every processor.

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BCD (8421), Gray code (only one bit changes between successive values, which is why it is used in shaft encoders and K-maps), excess-3, and ASCII (8.5).

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Gate Symbol expression Behaviour NOT (inverter) Y = A′ Output is the complement of the input AND Y = A·B Output 1 only when all inputs are 1 (the 'all or nothing' gate) OR Y = A + B Output 1 when any input is 1 NAND Y = (A·B)′ AND followed by NOT; output 0 only when all inputs are 1.

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Universal gate NOR Y = (A + B)′ OR followed by NOT; output 1 only when all inputs are 0.

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Universal gate XOR (exclusive-OR) Y = A ⊕ B = A′B + AB′ Output 1 when the inputs are different; for many inputs it gives 1 for an odd number of 1s — the odd-parity generator and inequality detector XNOR (equivalence) Y = (A ⊕ B)′ = AB + A′B′ Output 1 when the inputs are the same — the equality/coincidence detector, used in comparators • Universal gates:

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NAND and NOR can each realise any logic function, because each can be configured as a NOT (tie the inputs together), an AND and an OR.

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This matters practically because a single gate type simplifies fabrication and inventory, and NAND is the fastest and simplest gate to make in CMOS. • Logic families:

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TTL (fast, robust, but higher power), CMOS (near-zero static power, wide supply range, high noise immunity, high density — now dominant), and ECL (very fast, high power).

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Key parameters are propagation delay, power dissipation, fan-in and fan-out, noise margin and the power-delay product.

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Theorems and Simplification • Basic laws: commutative (A + B = B + A;

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AB = BA), associative, distributive (A(B + C) = AB + AC and, uniquely in Boolean algebra, A + BC = (A + B)(A + C)). • Identity and null:

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A + 0 = A, A·1 = A, A + 1 = 1, A·0 = 0. • Idempotent and complement:

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A + A = A, A·A = A, A + A′ = 1, A·A′ = 0, and involution (A′)′ = A. • Absorption:

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A + AB = A and A(A + B) = A; and the important variants A + A′B = A + B and A(A′ + B) = AB. • Consensus theorem:

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AB + A′C + BC = AB + A′C — the third term is redundant. • De Morgan's laws, the most used of all:

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(A·B)′ = A′ + B′ and (A + B)′ = A′·B′ — the complement of a product is the sum of the complements, and vice versa.

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Practically, 'break the bar and change the sign', and the laws are what allow any circuit to be converted into NAND-only or NOR-only form. • Canonical forms: the sum of products (SOP), a sum of minterms (each minterm being a product term that is 1 for exactly one input combination), and the product of sums (POS), a product of maxterms.

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A truth table converts directly into SOP by writing a minterm for every row whose output is 1.

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The Karnaugh Map • A Karnaugh map is a graphical arrangement of a truth table in which adjacent cells differ by only one variable — the rows and columns being labelled in Gray code (00, 01, 11, 10) for exactly this reason.

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Simplification then becomes a matter of recognising rectangles rather than manipulating algebra. • Size:

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2 variables = 4 cells, 3 variables = 8 cells, 4 variables = 16 cells; beyond about five or six variables the method becomes unwieldy and the Quine-McCluskey tabular method or software is used. • Rules for grouping:

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(1) group only 1s (for SOP) that are adjacent, including wrap-around at the edges and the four corners, since the map is topologically a torus;

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(2) each group must contain a number of cells that is a power of two — 1, 2, 4, 8 or 16;

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(3) groups must be as large as possible, because each doubling of group size eliminates one variable;

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(4) use as few groups as possible, but every 1 must be covered at least once;

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(5) groups may overlap; and (6) don't-care conditions (X) may be included in a group if they help make it larger, or ignored if they do not. • Reading the result: within a group, the variables that change across the group are eliminated, and those that remain constant are written — uncomplemented if constant at 1 and complemented if constant at 0.

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A group of 2 cells eliminates one variable, a group of 4 eliminates two, a group of 8 eliminates three. • Terminology: a prime implicant is a group that cannot be made larger; an essential prime implicant is one that covers at least one 1 that no other group covers, and must therefore appear in the final expression. • Why simplify: fewer gates and gate inputs mean lower cost, less power, less board area, shorter propagation delay and higher reliability; grouping also removes the static hazards that cause momentary false outputs when inputs change.

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This section covers half and full adders, half and full subtractors, encoders and decoders, and multiplexers and demultiplexers.

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Combinational versus Sequential Logic In a combinational circuit the output depends only on the present combination of inputs; there is no memory and no feedback.

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In a sequential circuit (8.3) the output depends on the present inputs and on the past history stored in memory elements.

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Design of a combinational circuit proceeds from problem statement → truth table → Boolean expression → simplification (K-map) → logic diagram.

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Adders • Half adder: adds two single bits A and B and produces a sum and a carry.

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Sum S = A ⊕ B (an XOR gate) and Carry C = A·B (an AND gate).

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Its limitation — and the reason for the full adder — is that it has no provision for a carry coming in from a previous stage, so it cannot be cascaded. • Full adder: adds three bits, A, B and a carry-in.

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Sum S = A ⊕ B ⊕ Cin and Carry-out Cout = AB + BCin + ACin = AB + Cin(A ⊕ B).

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It can be built from two half adders and one OR gate. • Multi-bit addition: cascading n full adders gives a ripple carry adder, whose drawback is that the carry must propagate through every stage, so the delay grows with n; the carry look-ahead adder computes the carries in parallel from generate and propagate terms and is much faster, at the cost of more logic.

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Subtractors • Half subtractor: subtracts B from A.

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Difference D = A ⊕ B — the same expression as the half adder sum — and Borrow Bout = A′·B.

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Note the complemented A, which is the only difference from the adder's carry. • Full subtractor: takes a borrow-in as well.

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Difference D = A ⊕ B ⊕ Bin and Borrow Bout = A′B + Bin(A ⊕ B)′. • In practice, dedicated subtractors are rarely built: subtraction is performed by adding the 2's complement of the subtrahend, so the same adder hardware serves for both, with an XOR gate on each B input acting as a controlled inverter and the mode control also supplying the initial carry-in — the standard adder/subtractor circuit.

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Encoders and Decoders • Encoder: converts 2ⁿ (or fewer) input lines into an n-bit coded output, so it is the 'many to few' device — for example an 8-to-3 or a decimal-to-BCD (10-to-4) encoder.

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The ordinary encoder assumes only one input is active at a time; if two are active the output is meaningless, which is why the priority encoder exists — it responds to the highest-priority active input and ignores the others, and also provides a valid output indicator to distinguish 'no input active' from 'input 0 active'.

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Applications: keyboards, interrupt controllers and, in medical equipment, alarm and keypad encoding. • Decoder: the inverse, converting an n-bit code into one of 2ⁿ outputs, activating exactly one — a 2-to-4, 3-to-8 or 4-to-16 decoder, or the BCD-to-seven-segment decoder used for every numeric display on a medical instrument.

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Decoders with an enable input can be used for memory address decoding and chip select, which is their commonest role, and a decoder plus OR gates can implement any combinational function directly from its minterms.

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Multiplexers and Demultiplexers • Multiplexer (MUX, data selector): selects one of 2ⁿ input lines and routes it to a single output, according to n select (control) lines — 'many to one'.

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Thus a 4-to-1 MUX has 2 select lines and an 8-to-1 MUX has 3; the general relation, frequently examined, is 2ⁿ inputs require n select lines.

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Most devices also have an enable. • Applications of the multiplexer: data routing and source selection; parallel-to-serial conversion; time-division multiplexing of several signals onto one line or one ADC — which is exactly how a multi-channel patient monitor or EEG machine digitises many channels with a single converter (5.2); waveform generation; and implementing any combinational logic function of n variables with a 2ⁿ-to-1 multiplexer by connecting the variables to the select lines and the required minterm values to the data inputs. • Demultiplexer (DEMUX, data distributor): the inverse — one input routed to one of 2ⁿ outputs chosen by n select lines, 'one to many'.

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Used for data distribution, serial-to-parallel conversion, and reconstructing the separate channels at the receiving end of a multiplexed link.

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A demultiplexer and a decoder are essentially the same circuit: a decoder with an enable input is a demultiplexer, with the enable serving as the data input — a point examiners like. • Other standard combinational blocks: the magnitude comparator (built from XNOR gates, giving A > B, A = B and A < B), the parity generator and checker (built from XOR gates — 8.5), and code converters such as binary-to-Gray and BCD-to-binary.

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This section covers the SR, D, JK, T and master-slave flip-flops with their symbols, logic diagrams and truth tables, and the four types of shift register together with counters.

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Latches and Flip-Flops • A flip-flop is a bistable device that stores one bit, the basic memory element of every sequential circuit.

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The distinction from a latch is that a latch is level-triggered — transparent while the enable is active — whereas a flip-flop is edge-triggered, changing state only on the rising or falling edge of a clock, which is what makes synchronous design possible. • Triggering may be by positive (rising) edge, negative (falling) edge or level; the symbol shows a triangle at the clock input, with a bubble for negative-edge triggering.

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Most devices also have asynchronous preset and clear inputs that override the clock. • Timing parameters worth knowing: setup time (the data must be stable before the clock edge), hold time (and stable after it), propagation delay, and the resulting maximum clock frequency; violating setup or hold times causes metastability.

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Flip-flop Inputs and characteristic equation Behaviour SR (set-reset) Qnext = S + R′Q S = 0, R = 0 → no change;

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S = 0, R = 1 → reset;

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S = 1, R = 1 → forbidden (invalid/race) state, since both outputs would go to the same level.

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Built from cross-coupled NOR (or NAND) gates D (data/delay) Qnext = D The output simply takes the value of D at the clock edge — the forbidden state is removed by deriving R from S through an inverter.

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The workhorse of registers and data storage JK Qnext = JQ′ + K′Q Removes the forbidden state of the SR flip-flop:

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J = K = 0 no change, J = 1 K = 0 set, J = 0 K = 1 reset, and J = K = 1 TOGGLES (the output complements).

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The most versatile flip-flop T (toggle) Qnext = TQ′ + T′Q = T ⊕ Q Formed by tying J and K together:

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T = 0 no change, T = 1 toggle.

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The basic element of ripple counters and frequency dividers Master-slave Two flip-flops in cascade The master is enabled while the clock is high and the slave while it is low, so data is accepted on one level and transferred to the output on the opposite one.

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Its purpose is to prevent the race-around condition of a level-triggered JK flip-flop with J = K = 1, in which the output would oscillate repeatedly while the clock remained high • Race-around is the standard examination point: in a level-triggered JK flip-flop with J = K = 1, the output toggles, feeds back and toggles again, so it oscillates as long as the clock pulse lasts, and the final state is indeterminate.

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It occurs when the clock pulse width is greater than the propagation delay.

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The remedies are to make the pulse shorter than the propagation delay (impractical), or to use edge triggering, or — the classical solution — to use the master-slave configuration. • Applications of flip-flops: data storage and registers, counters and frequency division (one flip-flop divides the frequency by two), shift registers, bounce elimination for mechanical switches, synchronisation of asynchronous inputs, and as the storage cell of static RAM.

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Shift Registers • A register is a group of flip-flops storing a multi-bit word; a shift register also moves the data one position at each clock pulse.

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An n-bit register requires n flip-flops — a relation that is frequently asked. • The four configurations, defined by how data enters and leaves:

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Type Operation Use SISO — serial in, serial out Data enters one bit at a time and leaves one bit at a time; n clock pulses to load and n more to read out Time delay element, serial data buffering SIPO — serial in, parallel out Data is clocked in serially (n pulses) and all bits appear simultaneously at the outputs Serial-to-parallel conversion — the receiving end of a serial link (8.5) PISO — parallel in, serial out All bits are loaded at once, then shifted out one at a time (n pulses) Parallel-to-serial conversion — the transmitting end of a serial link PIPO — parallel in, parallel out All bits loaded and read simultaneously, in one clock pulse Temporary storage register; the fastest of the four Bidirectional / universal Shifts left or right under a direction control; the universal shift register does all four modes General-purpose data manipulation • Applications of shift registers: serial-to-parallel and parallel-to-serial conversion (the heart of every UART — 8.5), time delay, sequence generation, ring and Johnson counters, arithmetic shifting (a left shift multiplies by two and a right shift divides by two), pseudo-random sequence generation with feedback (LFSR), and digital filter delay lines — the z⁻¹ elements of the FIR filters of 8.6.

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Counters • A counter is a sequential circuit that progresses through a defined sequence of states, and is the commonest application of flip-flops. • Asynchronous (ripple) counters: the output of each flip-flop clocks the next, so the flip-flops do not change simultaneously.

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They are simple and use little hardware but are slow, because the delay accumulates through the chain, and they produce transient false states (glitches) during the ripple. • Synchronous counters: all flip-flops are clocked together by a common clock, with combinational logic determining which should toggle.

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They are faster and free of ripple glitches, at the cost of more logic — and are the standard choice. • Modulus: an n-flip-flop counter has a natural modulus of 2ⁿ, so 4 flip-flops count 0 to 15 (mod 16).

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A mod-N counter requires the smallest n such that 2ⁿ ≥ N, with feedback to reset at N — hence the decade (mod-10) counter needs 4 flip-flops.

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Counters may be up, down or up/down, and special types are the ring counter (a circulating single 1, n states for n flip-flops) and the Johnson (twisted-ring) counter (2n states). • Uses in medical equipment: frequency division and timing, event and pulse counting (as in the radiation counters of 4.6 and the cell counters of 5.5), digital clocks and timers, frequency measurement, and the address and control sequencing inside every microprocessor system.

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This section covers static and dynamic memory, the types of read/write and read-only memory, and programmable logic devices including the PAL and PLA.

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Memory Fundamentals • Organisation: memory is an array of storage cells addressed by an address bus and accessed through a data bus with control signals (read/write, chip select, output enable).

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Capacity is expressed as number of locations × word size, and n address lines address 2ⁿ locations — so 10 lines give 1 K, 16 lines 64 K and 20 lines 1 M.

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This is one of the most reliably examined relations in the chapter. • Classification: by volatility — volatile memory loses its contents when power is removed (RAM), non-volatile retains them (ROM, flash); by access — random access (any location in the same time) versus sequential (tape); and by function — read/write versus read-mostly or read-only. • The memory hierarchy, from fastest and smallest to slowest and largest: registers → cache → main memory → secondary storage. • Key parameters: access time, cycle time, capacity, cost per bit, power consumption, volatility and endurance (write cycles).

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Static RAM (SRAM) Dynamic RAM (DRAM) Storage cell A flip-flop (typically 6 transistors) A capacitor with one access transistor — charge present = 1 Refresh Not required while power is applied Must be refreshed every few milliseconds, because the capacitor leaks — requiring refresh circuitry Speed Fast Slower Density and cost Low density, expensive per bit High density, cheap per bit Power Higher static power; but very low in standby (CMOS) Lower per bit, though refresh consumes power Typical use Cache memory, registers, small embedded systems and battery-backed memory in medical instruments Main memory of computers Volatility Volatile Volatile Read-Only Memory and its Variants Type Programming Erasure Use ROM (mask ROM) Programmed by the manufacturer during fabrication Impossible High-volume fixed code; cheapest per bit in quantity but no flexibility and a long lead time PROM Programmed once by the user, by blowing fusible links Impossible — one-time programmable Small production runs and prototypes EPROM Electrically programmed by the user (charge trapped on a floating gate) Erased by ultraviolet light through a quartz window, 15-20 minutes, erasing the whole chip Development work; now largely obsolete EEPROM Electrically programmed Electrically erasable, byte by byte, in circuit Storing calibration constants, configuration and patient settings in instruments; limited endurance (10⁴-10⁶ cycles) Flash Electrically programmed Electrically erasable in blocks/sectors — much faster than EEPROM Firmware, solid-state storage, memory cards; the dominant non-volatile memory • The examinable distinctions:

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EPROM is erased by ultraviolet light and only as a whole;

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EEPROM is erased electrically and can be done byte by byte without removing the chip; flash is electrically erased but in blocks, which is what makes it fast and dense.

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All three store charge on a floating gate, and all are non-volatile with a finite number of write cycles. • Other memory:

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NVRAM (SRAM with a battery), FRAM and MRAM (fast non-volatile alternatives used in implantable and low-power devices), and cache, buffer and scratchpad memories.

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Programmable Logic Devices • A programmable logic device contains an array of gates whose interconnections the user programs, so that a custom logic function can be implemented in one chip instead of many discrete gates.

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The advantages are reduced board area and component count, fewer interconnections and therefore higher reliability, design security, and the ability to change the design without changing the board. • All the simple devices are built on the same structure — an AND array followed by an OR array, implementing a sum-of-products expression — and they differ only in which array is programmable:

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Device AND array OR array Remarks PROM Fixed (a full decoder) Programmable All 2ⁿ minterms are generated; flexible for arbitrary truth tables but wasteful for sparse functions PAL (programmable array logic) Programmable Fixed Faster and cheaper than the PLA and much the commonest; each OR gate is permanently connected to a fixed group of product terms, so product terms cannot be shared between outputs PLA (programmable logic array) Programmable Programmable The most flexible of the three, since product terms can be shared between several outputs, but slower and more expensive; sometimes called a field-programmable logic array • Complex devices:

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CPLD (many PAL-like blocks with a programmable interconnect) and FPGA (an array of configurable logic blocks, look-up tables, flip-flops, memory and DSP blocks with a rich routing fabric) — the latter being reprogrammable, capable of implementing whole systems, and the standard route for medical device prototyping and for signal-processing hardware such as ultrasound beamformers and CT reconstruction front ends.

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At the other end, an ASIC is fully custom: the lowest power, size and unit cost at high volume, and the technology of pacemakers, hearing aids and implantable devices, but with a very high development cost and no flexibility. • Design flow: description in a hardware description language (VHDL or Verilog) → simulation → synthesis → place and route → programming and verification.

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This section covers the ASCII code, asynchronous serial transmission with start, stop and parity bits and baud rate, synchronous transmission, and the physical communication standards used to connect medical equipment.

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Serial and Parallel Transmission • Parallel transmission sends all bits of a word simultaneously on separate lines — fast but needing many conductors, and limited in distance by skew and crosstalk; it is used inside equipment (the data bus).

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Serial transmission sends bits one after another on a single line — slower per bit but needing only one or two conductors, and far better over distance; it is used for every external link and is what this section describes. • Direction: simplex (one way only), half duplex (both ways but not at once) and full duplex (both ways simultaneously).

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The ASCII Code • ASCII (American Standard Code for Information Interchange) is the standard code for representing characters as binary.

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It is a 7-bit code giving 2⁷ = 128 characters, commonly stored or transmitted in 8 bits with the eighth used for parity or to give the extended 256-character set. • Structure: codes 0-31 and 127 are control characters (such as LF = 10, CR = 13, ESC = 27), and 32-126 are printable.

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Useful landmarks: space = 32, '0' = 48, 'A' = 65, 'a' = 97 — so the decimal digits are 48 to 57, and lower case is 32 more than upper case, meaning case is changed by flipping a single bit. • Other codes:

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EBCDIC (IBM, 8-bit), Unicode/UTF-8 (which extends ASCII to all writing systems and is what modern systems actually use), and BCD and Gray code for numeric and positional data.

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Asynchronous Serial Transmission • In asynchronous transmission, transmitter and receiver do not share a clock; instead each character is framed by its own start and stop bits, and the receiver resynchronises at the beginning of every character.

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The line is therefore idle for arbitrary periods between characters, which suits keyboards, terminals and instruments that send data sporadically. • The frame: the line rests in the mark (logic 1) state.

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Transmission begins with one start bit, which is always a 0 (space) — its falling edge tells the receiver when to start sampling; then 5 to 8 data bits, sent least significant bit first; then an optional parity bit; then 1, 1.5 or 2 stop bits, always logic 1, which guarantee a transition at the start of the next character and give the receiver time to process.

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The common configuration is written 8N1 — eight data bits, no parity, one stop bit. • Overhead is the point to remember: with 8N1, 10 bits are transmitted for every 8 bits of data, so only 80 % of the line capacity carries information — at 9,600 baud that is 960 characters per second. • Baud rate versus bit rate: the baud rate is the number of signalling elements (symbol changes) per second, while the bit rate is the number of bits per second.

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They are equal only when each symbol carries one bit, which is the case for simple two-level signalling; with multi-level or phase modulation (as in a modem) one symbol can carry several bits, so the bit rate exceeds the baud rate.

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Standard rates are 300, 1,200, 2,400, 9,600, 19,200, 38,400 and 115,200.

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Both ends must be set to the same speed, data length, parity and stop bits, or the data will be garbled. • Parity is the simplest error check: a bit is added to make the total number of 1s even (even parity) or odd (odd parity).

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It is generated and checked with XOR gates.

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Its limitation is fundamental: parity detects any odd number of bit errors but cannot detect an even number, and it cannot correct anything.

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Serious links therefore use checksums, CRC or Hamming codes.

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Other detected conditions are the framing error (the stop bit is not found where expected — usually a baud-rate mismatch) and the overrun error (a character arrives before the previous one has been read). • The UART (universal asynchronous receiver/transmitter) performs all of this in hardware: on transmission it takes a parallel byte, adds start, parity and stop bits and shifts it out (a PISO shift register — 8.3); on reception it detects the start bit, samples each bit at its centre using a clock typically 16 times the baud rate, checks parity, removes the framing and presents a parallel byte (a SIPO register), raising an interrupt.

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A USART can also work synchronously.

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Synchronous Transmission • In synchronous transmission, transmitter and receiver are locked to a common clock — either carried on a separate line, or recovered from the data stream itself by using a self-clocking code such as Manchester encoding.

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Data is sent as a continuous block or frame of many characters, preceded by SYN characters or a flag and followed by a CRC, with no start and stop bits around each character. • Comparison, which is the standard examination question: synchronous transmission has far lower overhead and therefore much higher efficiency and speed, and is used for bulk data; asynchronous transmission is simpler and cheaper, needs no clock recovery, tolerates irregular timing between characters, and is used for low-speed intermittent data — but its per-character framing wastes 20 % or more of the capacity.

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Synchronous links require more complex hardware and lose synchronisation badly if the clock slips.

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Physical Communication Standards Standard Characteristics RS-232 (EIA-232) The classic point-to-point serial standard: single-ended (unbalanced) signalling referred to a common ground, ±3 to ±15 V with negative voltage representing logic 1 (mark) and positive logic 0; limited to about 15 m and 20 kbit/s (in practice more);

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9-pin or 25-pin connector.

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Still ubiquitous on laboratory and medical instruments RS-422 / RS-485 Differential (balanced) signalling on a twisted pair, giving excellent noise immunity over 1,200 m at high data rates;

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RS-485 is multi-drop, supporting up to 32 devices on one bus — used in building and equipment networks USB Differential pair plus power; hot-pluggable, host-controlled, with several speed grades; the standard interface for modern instruments and for connecting devices to a PC Ethernet (IEEE 802.3) and TCP/IP The basis of hospital networks, PACS (4.5) and central monitoring (5.2) I²C and SPI Short-distance on-board buses between a microcontroller and its sensors and peripherals — I²C uses two wires with addressing, SPI four wires with chip select and higher speed CAN bus Robust differential multi-master bus with error handling, used inside complex equipment such as imaging systems and ventilators Bluetooth, BLE, Zigbee, Wi-Fi Wireless links for telemetry, wearables and implants (5.3) HL7, DICOM, IEEE 11073 Not physical layers but the data and interoperability standards that give the bits their meaning — DICOM for images (4.5), HL7 for clinical data, and IEEE 11073 for point-of-care medical device communication • In medical equipment the physical layer must also satisfy the patient isolation requirements of 6.6: data crossing to a patient-connected circuit passes through optocouplers, isolation transformers, digital isolators or a fibre-optic link, and the interface must be designed so that no fault can raise the leakage current beyond the permitted limit.

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This section covers the four filter responses — low-pass, high-pass, band-pass and band-stop (notch) — their characteristics, implementation and their specific applications in biomedical signal processing.

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Filter Fundamentals • A filter passes signals in one range of frequencies (the passband) and attenuates those in another (the stopband), the two separated by a transition band.

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The boundary is the cut-off frequency fc, defined as the −3 dB point, where the output power has fallen to half and the voltage to 0.707 of its passband value. • Specifications: passband ripple, stopband attenuation, transition width, roll-off rate (20n dB per decade for an n-th order filter, or 6n dB per octave), and phase response and group delay — the last being critical for biosignals, because unequal delay of different frequency components distorts the shape of a waveform such as the QRS complex even when the amplitude response is correct. • Implementation: passive (R, L, C — no gain, loading, bulky inductors at low frequency), active (op-amp with R and C — gain, buffering, no inductors, cascadable; the Sallen-Key and multiple-feedback topologies of 7.2), switched-capacitor (clock-tunable, on-chip) and digital. • Digital filters deserve emphasis because modern instruments filter in software:

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FIR (finite impulse response) filters use only past inputs, are always stable and can be given exactly linear phase — which is why they are preferred for the ECG and other biosignals, at the cost of needing a high order;

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IIR (infinite impulse response) filters use feedback, achieve a given sharpness with a far lower order and less computation, but have non-linear phase and can be unstable.

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Both are built from the delay (z⁻¹), multiply and add elements, the delay being the shift register of 8.3.

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Filter Passes Attenuates Simplest form Low-pass (LPF) All frequencies below fc, including DC Everything above fc Series R with shunt C (output across C) High-pass (HPF) All frequencies above fc Everything below, including DC Series C with shunt R (output across R) Band-pass (BPF) A band between fL and fH Everything outside that band LPF and HPF in cascade, or a series resonant circuit Band-stop / notch (BSF) Everything except a narrow band A narrow band around f₀ LPF and HPF in parallel summed, or a twin-T network • For the simple RC sections, fc = 1/(2πRC).

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For band-pass and band-stop responses, the centre frequency f₀ = √(fL·fH), the bandwidth BW = fH − fL, and the quality factor Q = f₀/BW — so a high Q means a narrow, sharply selective band, which is exactly what a mains notch filter requires.

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Applications in Biomedical Signal Processing • Every biopotential amplifier contains a filter chain, and the values follow directly from the signal bandwidths of 5.1. • High-pass filtering removes the DC offset of the electrode half-cell potential and the low-frequency baseline wander caused by respiration, movement and perspiration.

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For the diagnostic ECG the standard is 0.05 Hz, chosen deliberately low because a higher corner distorts the ST segment and the T wave and could cause a myocardial infarction to be missed; monitoring mode uses 0.5 Hz, accepting that distortion in exchange for a much more stable baseline. • Low-pass filtering removes high-frequency noise, EMG (muscle tremor) artefact and radio-frequency interference.

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The diagnostic ECG upper limit is 100-150 Hz (higher in paediatrics, to capture narrow QRS complexes and pacemaker spikes), while monitoring mode uses 40 Hz.

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A low-pass filter is also mandatory as the anti-aliasing filter before every ADC, set below half the sampling rate as required by the Nyquist criterion — an omission that cannot be corrected afterwards, since aliased components are indistinguishable from real signal. • Band-pass filtering is simply the combination of the two, and defines the working band of each modality:

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ECG 0.05-100 Hz, EEG 0.5-70 Hz, EMG 10-2,000 Hz, phonocardiogram 20-2,000 Hz.

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Narrow band-pass filters are also used inside algorithms — the 10-25 Hz band-pass stage of the Pan-Tompkins QRS detector (5.2) is the standard example, chosen because the QRS complex has most of its energy there while P and T waves and baseline wander lie below and muscle noise above. • Band-stop (notch) filtering is used almost exclusively for one purpose: rejecting 50 Hz (or 60 Hz) mains interference and its harmonics.

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It must be very narrow (high Q), because the ECG and EEG contain genuine signal at 50 Hz; a wide notch removes diagnostic information and, in the ECG, blunts the QRS and can produce ringing artefacts that mimic pathology.

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For this reason a notch filter is the last resort, not the first — the proper remedies are a high CMRR amplifier, a driven right-leg circuit, good electrode contact with balanced impedance, shielded twisted leads and removal of the interference source, exactly as set out in 5.1.

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Adaptive notch filters that track the mains frequency and subtract a synthesised interference waveform are the modern solution. • Other filtering applications across the paper: the ripple filters of a power supply (7.4); the tuned circuits of transmitters and receivers (7.2, 5.3); wall filters in Doppler ultrasound, which are high-pass filters removing the very large low-frequency signal from slowly moving vessel walls so that the much smaller blood-flow signal can be seen (4.4); reconstruction and k-space filtering in MRI and CT (4.2, 4.3); image smoothing and sharpening as two-dimensional low-pass and high-pass operations;

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EEG band separation into delta, theta, alpha and beta (5.1); and anti-aliasing and reconstruction filters around every converter.