Digital Logic and Microprocessor

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This section covers number systems and conversions, logic levels and logic gates, Boolean algebra, and the use of Sum-of-Products, Product-of-Sums and Karnaugh maps to simplify logic expressions.

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Number Systems & Conversions System Base (Radix) Digits Used Binary 2 0, 1 Octal 8 0–7 Decimal 10 0–9 Hexadecimal 16 0–9, A–F Decimal → Binary: repeated division by 2, collecting remainders in reverse.

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Binary → Decimal: sum of (bit value × 2position) for every ‘1’ bit, e.g.

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1101₂ = 1×23+1×22+0×21+1×20 = 13.

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Each hexadecimal digit maps exactly to 4 binary bits (a nibble); each octal digit maps to 3 binary bits.

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Logic Levels & Logic Gates Positive logic:

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HIGH = logic 1, LOW = logic 0.

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Negative logic: the reverse assignment.

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Gate Function Output is HIGH when… AND Y = A·B ALL inputs are HIGH OR Y = A+B AT LEAST ONE input is HIGH NOT Y = A’ The single input is LOW (inverter) NAND Y = (A·B)’ AT LEAST ONE input is LOW — a universal gate NOR Y = (A+B)’ ALL inputs are LOW — a universal gate XOR Y = A⊕B Inputs are DIFFERENT (odd number of 1s) XNOR Y = (A⊕B)’ Inputs are the SAME NAND and NOR are universal gates — any Boolean function (AND, OR, NOT) can be built using only NAND gates, or only NOR gates.

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Boolean Algebra & Simplification Key laws:

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Commutative (A+B=B+A), Associative, Distributive (A(B+C)=AB+AC), Identity (A+0=A, A·1=A), Idempotent (A+A=A).

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De Morgan’s theorems:

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(A+B)’ = A’·B’, and (A·B)’ = A’+B’.

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SOP (Sum of Products): a Boolean expression written as an OR of AND terms, e.g.

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POS (Product of Sums): a Boolean expression written as an AND of OR terms, e.g.

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Truth table → Karnaugh map (K-map): a graphical grid method that groups adjacent 1s (for SOP) or 0s (for POS) in powers of two to derive the minimal Boolean expression, avoiding lengthy algebraic manipulation.

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This section covers multiplexers, demultiplexers, decoders, encoders, binary addition and subtraction, and the representation of unsigned and signed binary numbers.

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Multiplexers & Demultiplexers A multiplexer (MUX) is a many-to-one combinational circuit: it selects one of 2ⁿ data inputs and routes it to a single output, based on n select lines (a 2ⁿ:1 MUX).

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A demultiplexer (DEMUX) performs the opposite function: it routes a single data input to one of 2ⁿ outputs, based on n select lines.

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Decoders & Encoders A decoder converts n coded input lines into up to 2ⁿ unique, mutually-exclusive output lines (e.g., a 3-to-8 line decoder).

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An encoder performs the reverse: it converts one of 2ⁿ active input lines into an n-bit coded output.

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A priority encoder resolves the case where multiple inputs are active simultaneously by encoding only the highest-priority active input.

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Binary Addition & Subtraction Circuit Inputs Outputs Half adder A, B (2 bits, no carry-in) Sum = A⊕B;

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Carry = A·B Full adder A, B, Carry-in (C_in) Sum = A⊕B⊕C_in;

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Carry-out = AB + BC_in + AC_in Multi-bit binary addition is performed by cascading full adders (a ripple-carry adder), with each stage’s carry-out feeding the next stage’s carry-in.

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Binary subtraction is normally performed by adding the 2’s complement of the subtrahend to the minuend — this lets the same adder hardware perform both addition and subtraction.

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Unsigned & Signed Binary Numbers Representation Rule Sign-magnitude MSB = sign bit (0=+, 1=−); remaining bits = magnitude 1’s complement Negative numbers formed by inverting every bit of the positive value 2’s complement Negative numbers formed by inverting every bit, then adding 1 — the standard representation in modern computers Range of an n-bit unsigned number:

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Range of an n-bit 2’s complement signed number: −2ⁿ⁻¹ to +2ⁿ⁻¹−1 (e.g., 8-bit: −128 to +127).

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2’s complement has only one representation of zero (unlike 1’s complement and sign-magnitude, which each have two: +0 and −0).

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This section covers flip-flop types (RS, gated, edge-triggered, master-slave), registers and shift-register applications, and asynchronous vs synchronous counters.

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Flip-Flop Types Type Behaviour RS (SR) flip-flop S=1,R=0 → Set (Q=1);

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S=0,R=1 → Reset (Q=0);

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S=R=1 → invalid/undefined Gated (clocked) flip-flop Responds to inputs only while the clock is at its active LEVEL (level-triggered) Edge-triggered flip-flop Responds to inputs only at the clock’s rising or falling EDGE (more precise timing) Master-slave flip- flop Two latches in cascade (master captures on one clock phase, slave releases on the other) — eliminates the JK flip-flop’s race-around condition JK flip-flop: like SR but J=K=1 causes the output to toggle (avoiding the SR invalid state).

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D flip-flop: output simply follows the D input at the active clock edge — used for data storage/latching.

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T (toggle) flip-flop: output toggles on every active clock edge when T=1 — the basic building block of counters.

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Registers & Shift Registers Shift Register Type Data In / Data Out SISO Serial In, Serial Out SIPO Serial In, Parallel Out PISO Parallel In, Serial Out PIPO Parallel In, Parallel Out Applications: serial-to-parallel / parallel-to-serial data conversion (e.g., UARTs), temporary data storage, delay lines, and ring/Johnson counters.

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Counters Counter Type Operation Asynchronous (ripple) Only the first flip-flop is clocked externally; each subsequent stage is triggered by the previous stage’s output — simple but has cumulative propagation delay Synchronous All flip-flops are triggered by the same common clock simultaneously — faster, no ripple delay, but needs more control logic

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This section covers the internal architecture and key features of a microprocessor, and the basics of assembly language programming.

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Internal Architecture of a Microprocessor Block Function ALU (Arithmetic & Logic Unit) Performs arithmetic and logical operations on data Control Unit (CU) Generates timing and control signals that coordinate all operations Accumulator General-purpose register holding operands and results of ALU operations Program Counter (PC) Holds the address of the NEXT instruction to be fetched Instruction Register (IR) Holds the instruction currently being decoded/executed Stack Pointer (SP) Holds the address of the top of the stack (used for subroutine calls, interrupts) General-purpose registers Temporary on-chip storage for data/addresses, faster than memory access Three main buses:

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Data bus (bidirectional, carries data), Address bus (unidirectional, carries memory/IO addresses), Control bus (carries control/timing signals such as Read, Write, Reset).

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Key features that characterize a microprocessor: word length (bits processed at once, e.g., 8/16/32/64-bit), clock speed, instruction set, addressing modes, and number of registers.

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Fetch (get instruction from memory, pointed to by PC) → Decode (interpret the opcode) → Execute (perform the operation).

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Assembly Language Programming A mnemonic is a short symbolic name for a machine instruction (e.g., MOV, ADD, JMP), making assembly language far more readable than raw machine code (binary/hex opcodes).

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An assembler is the program that translates assembly-language source code (mnemonics) into machine code (binary).

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Common instruction categories: data transfer (MOV, LOAD, STORE), arithmetic/logic (ADD, SUB, AND, OR), branch/control (JMP, CALL, RET — alter the normal sequential flow), and I/O instructions.

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This section covers memory classification and hierarchy, I/O and memory interfacing, serial communication (synchronous/asynchronous), common serial standards, and DMA.

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Memory Classification & Hierarchy Memory Type Key Feature SRAM (Static RAM) Fast, no refresh needed, volatile; used for cache memory DRAM (Dynamic RAM) Needs periodic refresh, higher density/lower cost, volatile; used for main memory ROM / PROM / EPROM / EEPROM Non-volatile — retains data without power; used for firmware/boot code Memory hierarchy (fastest/smallest/costliest to slowest/largest/cheapest):

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CPU registers → cache memory → main memory (RAM) → secondary storage (disk).

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I/O & Memory Interfacing Memory-mapped I/O: peripherals occupy part of the regular memory address space; accessed with ordinary memory-read/write instructions.

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I/O-mapped (isolated) I/O: peripherals have a separate address space, accessed only with dedicated IN/OUT instructions.

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PPI (Programmable Peripheral Interface): a chip (e.g., the classic 8255) providing multiple programmable parallel I/O ports for connecting external devices to the microprocessor bus.

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Serial Interface Transmission Mode Description Synchronous Data synchronized to a shared clock signal; higher speed, no per-character framing overhead Asynchronous Each character framed with start and stop bits; no shared clock needed, simpler wiring Serial standards:

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RS232 (classic single-ended serial port, ±12V logic levels), RS423 (single-ended, improved over RS232), RS422 (differential, longer distance/higher noise immunity), USB (Universal Serial Bus — high speed, plug-and-play, supplies power too).

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USART (Universal Synchronous/Asynchronous Receiver Transmitter): a versatile serial communication IC/module supporting both synchronous and asynchronous modes.

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Direct Memory Access (DMA) DMA allows data to be transferred directly between memory and an I/O device, without the CPU handling every data word individually — greatly speeding up bulk transfers (e.g., disk I/O).

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A DMA controller manages the transfer: it requests bus control from the CPU (bus request/grant), then directly drives the address/data/control buses for the transfer duration.

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This final section of the chapter covers the concept of interrupts, how an interrupt service routine (ISR) is invoked and executed, and the overall interrupt processing sequence in a microprocessor system.

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Concept of Interrupt An interrupt is a signal (from hardware or software) that temporarily suspends the normal instruction sequence so the processor can respond to an event requiring immediate attention, then resumes the original program afterward.

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Hardware interrupts originate from external devices (e.g. a keyboard, timer, or peripheral needing service); software interrupts are triggered deliberately by an instruction within a program (e.g. for a system call).

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Interrupts may be maskable (can be selectively disabled/ignored by the processor) or non-maskable (cannot be disabled, reserved for critical events such as power failure).

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Interrupt Service Routine (ISR) An Interrupt Service Routine (ISR), also called an interrupt handler, is a special subroutine that executes in response to a specific interrupt, performing whatever action the event requires.

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The interrupt vector table stores the starting addresses of each ISR, indexed by interrupt type/number, so the processor knows where to jump for a given interrupt.

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Interrupt Processing Sequence Step Action 1.

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Interrupt request A device/instruction asserts an interrupt request signal 2.

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Complete current instruction The processor finishes executing its current instruction (interrupts are checked at instruction boundaries) 3.

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Save context Processor state (PC, flags, relevant registers) is pushed onto the stack so execution can later resume correctly 4.

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Fetch ISR address Processor looks up the appropriate ISR address via the interrupt vector table 5.

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Execute ISR The interrupt service routine runs, performing the required action 6.

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Restore context & return Saved state is popped from the stack (return-from-interrupt instruction) and normal program execution resumes exactly where it left off Interrupt priority: when multiple interrupts occur simultaneously (or one occurs during another's servicing), a priority scheme determines which is serviced first (or whether a lower-priority ISR can be interrupted by a higher-priority one — nested interrupts).

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Interrupts are generally more efficient than polling (repeatedly checking a device's status in software), since the CPU can perform other work until an event actually occurs.

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This section covers the CPU’s control unit and structure, microinstruction format, instruction formats and addressing modes, data transfer/manipulation, and the RISC vs CISC design philosophies including pipelining and parallel processing.

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Control Unit & CPU Structure The Control Unit (CU) generates the sequence of control signals that coordinate the ALU, registers, memory, and I/O during instruction execution.

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Hardwired control: control signals generated by fixed combinational logic — fast, but difficult to modify.

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Microprogrammed control: control signals generated by reading microinstructions stored in a small, fast control memory — slower but flexible/easily redesigned; each machine instruction maps to a sequence of microinstructions.

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CPU structure & function: the CPU integrates the ALU, control unit, and register set, connected internally by buses, to fetch, decode and execute instructions from memory.

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Instruction Formats & Addressing Modes An instruction format typically consists of an opcode (specifies the operation) and one or more operand/address fields.

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Addressing Mode Description Immediate The operand value itself is given directly in the instruction Direct The instruction gives the memory address of the operand Indirect The instruction gives the address of a memory location that itself holds the operand’s address Register The operand is held in a CPU register named by the instruction Indexed The effective address = a base address + the value in an index register Data Transfer & Manipulation Data transfer instructions move data between registers, memory, and I/O (e.g., MOV, LOAD, STORE) without altering its value.

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Data manipulation instructions (arithmetic, logic, shift) transform data via the ALU.

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RISC vs CISC, Pipelining & Parallel Processing Feature RISC CISC Instruction set Small, simple, uniform-length Large, complex, variable-length Execution Mostly single-cycle, register-based Multi-cycle, can operate directly on memory Design focus Optimized for pipelining/speed Optimized for code density/fewer instructions per program Examples ARM, MIPS, RISC-V x86 (Intel/AMD) Pipelining overlaps the stages (fetch, decode, execute, …) of successive instructions to increase instruction throughput.

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Structural (resource conflict), Data (an instruction needs a result not yet produced by a prior instruction), Control (caused by branches disrupting the fetch sequence).

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Parallel processing executes multiple instructions or tasks simultaneously (e.g., multiple execution units, multiple cores) to further increase throughput beyond what pipelining alone achieves.