ACtE/Chapter 4/Read MCQs
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Chapter 4 ยท MCQ Read Mode

Computer Organization and Embedded System

ACTE04ยท84 Total MCQs
Question 1 of 84Control & Central Processing Units

Hardwired control unit design is characterized by:

AMicroinstructions stored in control memory
BFixed combinational logic generating control signals
CBeing easily reprogrammed at runtime
DRequiring no logic circuits at all
Answer is hidden
Question 2 of 84Control & Central Processing Units

Microprogrammed control unit design generates control signals using:

AOnly hardwired logic gates
BA sequence of microinstructions stored in control memory
CExternal peripheral devices
DCache memory exclusively
Answer is hidden
Question 3 of 84Control & Central Processing Units

An instruction format typically consists of:

AOnly an address field
BAn opcode field and one or more operand/address fields
COnly data, no operation code
DA single bit
Answer is hidden
Question 4 of 84Control & Central Processing Units

In immediate addressing mode, the operand:

AIs found in a register
BIs given directly within the instruction itself
CRequires an extra memory access to locate
DIs always at a fixed memory address
Answer is hidden
Question 5 of 84Control & Central Processing Units

RISC architecture is generally characterized by:

AA large set of complex, variable-length instructions
BA small set of simple, fixed-length instructions
CNo use of registers
DExclusive use of microprogrammed control
Answer is hidden
Question 6 of 84Control & Central Processing Units

CISC architecture is generally characterized by:

ASimple fixed-length instructions only
BComplex, variable-length instructions that can operate directly on memory
CThe complete absence of a control unit
DMandatory single-cycle execution
Answer is hidden
Question 7 of 84Control & Central Processing Units

Pipelining in a CPU is used primarily to:

AReduce the latency of a single instruction
BIncrease overall instruction throughput by overlapping instruction stages
CEliminate the need for a control unit
DIncrease memory capacity
Answer is hidden
Question 8 of 84Control & Central Processing Units

A data hazard in a pipelined processor occurs when:

ATwo instructions require the same functional unit simultaneously
BAn instruction depends on the result of a previous instruction still in the pipeline
CThe control unit fails completely
DNo instructions are being executed
Answer is hidden
Question 9 of 84Control & Central Processing Units

Which technique helps mitigate data hazards in a pipeline?

AForwarding (bypassing)
BRemoving the ALU
CDisabling the control unit
DIncreasing instruction length arbitrarily
Answer is hidden
Question 10 of 84Control & Central Processing Units

Parallel processing differs from simple pipelining in that parallel processing:

AUses only a single functional unit
BExecutes multiple instructions/tasks simultaneously using multiple functional units or processors
CCannot be combined with pipelining
DAlways slows down execution
Answer is hidden
Question 11 of 84Computer Arithmetic & Memory System

Computer arithmetic operations (add, subtract) in the ALU typically use which number representation?

ASign-magnitude only
B2's complement
CBCD exclusively
DGray code
Answer is hidden
Question 12 of 84Computer Arithmetic & Memory System

In the memory hierarchy, which level is generally fastest and smallest?

ASecondary storage
BMain memory
CRegisters
DCache memory
Answer is hidden
Question 13 of 84Computer Arithmetic & Memory System

The memory hierarchy's effectiveness relies on the principle of:

ARandom access only
BLocality of reference (temporal and spatial)
CInfinite memory capacity
DZero access time everywhere
Answer is hidden
Question 14 of 84Computer Arithmetic & Memory System

In direct-mapped cache, each main memory block can be placed:

AIn any cache line
BIn exactly one specific cache line
CIn a set of cache lines
DNowhere; direct mapping bypasses cache
Answer is hidden
Question 15 of 84Computer Arithmetic & Memory System

Set-associative cache mapping is best described as:

AA pure direct-mapping scheme
BA compromise where a block maps to a specific set, and can go in any line within that set
CFully associative mapping only
DA scheme with no mapping function at all
Answer is hidden
Question 16 of 84Computer Arithmetic & Memory System

The LRU (Least Recently Used) algorithm is used in cache design to determine:

AWhich block to fetch first
BWhich block to evict when the cache is full
CThe cache's physical size
DThe write policy
Answer is hidden
Question 17 of 84Computer Arithmetic & Memory System

Write-through cache policy updates:

AOnly the cache, never main memory
BBoth the cache and main memory simultaneously on a write
CNeither the cache nor memory
DOnly main memory, bypassing cache
Answer is hidden
Question 18 of 84Computer Arithmetic & Memory System

Write-back cache policy updates main memory:

AImmediately on every write
BOnly when the modified cache block is evicted
CNever
DBefore the cache is even written
Answer is hidden
Question 19 of 84Computer Arithmetic & Memory System

ROM is classified, in terms of write ability and storage permanence, as:

ARead-write and volatile
BRead-only (or limited-write) and non-volatile
CRead-write and non-volatile like RAM
DNeither readable nor writable
Answer is hidden
Question 20 of 84Computer Arithmetic & Memory System

A split cache architecture separates:

AFast memory from slow memory only
BInstruction cache from data cache
CRAM from ROM
DRegisters from the ALU
Answer is hidden
Question 21 of 84I/O Organization & Multiprocessor

An I/O module's primary role is to:

AReplace the CPU entirely
BHandle the electrical/timing mismatch between the CPU/memory and peripherals
CStore the operating system permanently
DPerform only arithmetic operations
Answer is hidden
Question 22 of 84I/O Organization & Multiprocessor

Programmed I/O is characterized by:

AThe device interrupting the CPU when ready
BThe CPU actively polling the device status and transferring data itself
CDirect transfer without any CPU involvement
DNo data transfer occurring at all
Answer is hidden
Question 23 of 84I/O Organization & Multiprocessor

Interrupt-driven I/O improves on programmed I/O by:

AEliminating the need for any CPU involvement
BLetting the CPU do other work until the device signals it is ready
CRequiring the CPU to poll even more frequently
DRemoving the need for I/O modules
Answer is hidden
Question 24 of 84I/O Organization & Multiprocessor

DMA (Direct Memory Access) transfers data:

AThrough the CPU for every byte
BDirectly between device and memory, with minimal CPU involvement
COnly during system boot-up
DOnly using programmed I/O
Answer is hidden
Question 25 of 84I/O Organization & Multiprocessor

A multiprocessor system is defined by having:

AA single CPU with multiple caches
BMultiple CPUs sharing memory and I/O resources
CNo shared memory at all
DOnly one processing unit total
Answer is hidden
Question 26 of 84I/O Organization & Multiprocessor

A common bus interconnection structure in a multiprocessor system can become a:

ASource of infinite bandwidth
BBottleneck, since it is shared among processors
CMethod requiring no synchronization
DReplacement for all memory
Answer is hidden
Question 27 of 84I/O Organization & Multiprocessor

A crossbar switch interconnection provides:

AOnly sequential access
BAny-to-any connectivity between processors and memory modules, at higher cost
CNo connectivity at all
DConnectivity for exactly two processors only
Answer is hidden
Question 28 of 84I/O Organization & Multiprocessor

Inter-processor communication via shared memory relies on:

AExplicit message passing exclusively
BProcessors accessing a common address space
CNo communication mechanism at all
DEach processor having entirely isolated, non-shared memory
Answer is hidden
Question 29 of 84I/O Organization & Multiprocessor

Semaphores and locks in a multiprocessor system are used primarily to:

AIncrease clock speed
BSynchronize access to shared resources and prevent race conditions
CReplace the need for an interconnection network
DPerform arithmetic operations
Answer is hidden
Question 30 of 84I/O Organization & Multiprocessor

Message passing, as an inter-processor communication method, involves:

ADirect shared-memory access only
BExplicit send/receive operations over the interconnect
CNo communication between processors
DOnly DMA transfers
Answer is hidden
Question 31 of 84Hardware-Software Design in Embedded Systems

An embedded system is best described as:

AA general-purpose computer used for any task
BHardware and software combined to perform one or a few dedicated functions
CSoftware only, with no hardware component
DA standalone desktop operating system
Answer is hidden
Question 32 of 84Hardware-Software Design in Embedded Systems

A hard real-time embedded system is characterized by:

ANo timing requirements at all
BStrict deadlines that must never be missed
CFlexible deadlines that can occasionally be missed
DBeing identical to a general-purpose computer
Answer is hidden
Question 33 of 84Hardware-Software Design in Embedded Systems

A custom single-purpose processor, compared to a general-purpose processor, offers:

AMore flexibility but less speed
BHigher speed and efficiency for its specific task, but less flexibility
CIdentical performance in all cases
DNo advantage at all
Answer is hidden
Question 34 of 84Hardware-Software Design in Embedded Systems

An Application-Specific Instruction-Set Processor (ASIP) is designed to:

ABe completely general-purpose with no customization
BHave an instruction set customized for a particular application domain
CExecute only one fixed hardware function with no programmability
DReplace all memory hierarchies
Answer is hidden
Question 35 of 84Hardware-Software Design in Embedded Systems

The basic architecture of a custom single-purpose processor consists of:

AA general-purpose instruction fetch/decode unit only
BA datapath tailored to the algorithm, controlled by an FSM-based controller
COnly a memory unit with no control logic
DA standard microprocessor core unchanged
Answer is hidden
Question 36 of 84Hardware-Software Design in Embedded Systems

Optimizing a custom single-purpose processor can involve:

AAdding unnecessary functional units
BPipelining the datapath and removing unused functional units
CMaking the processor fully general-purpose
DRemoving all control logic
Answer is hidden
Question 37 of 84Hardware-Software Design in Embedded Systems

A cross-compiler is used in embedded development to:

ACompile code on the target device itself
BCompile code on a host machine for execution on a different target architecture
COnly debug hardware faults
DReplace the need for any compiler
Answer is hidden
Question 38 of 84Hardware-Software Design in Embedded Systems

JTAG interfaces are primarily used in embedded development for:

ACompiling source code
BIn-circuit debugging and testing on real hardware
CGenerating clock signals only
DReplacing the operating system
Answer is hidden
Question 39 of 84Hardware-Software Design in Embedded Systems

Classification of embedded systems by performance/time requirements distinguishes:

AOnly hardware types
BReal-time (hard/soft) vs non-real-time systems
COnly memory sizes
DOnly programming languages used
Answer is hidden
Question 40 of 84Hardware-Software Design in Embedded Systems

In a custom single-purpose processor, since behavior is implemented directly in hardware:

ATraditional software programming is required as in general-purpose systems
BThere is no traditional general-purpose programming; behavior is fixed by the hardware structure
CThe design cannot execute any algorithm
DIt always requires an operating system
Answer is hidden
Question 41 of 84Real-Time Operating & Control System

A process in an operating system is characterized by:

ASharing memory space with all other processes by default
BBeing an independent program in execution with its own memory address space
CAlways being identical to a thread
DNever being scheduled
Answer is hidden
Question 42 of 84Real-Time Operating & Control System

A thread differs from a process mainly in that a thread:

AHas its own completely separate memory space
BIs a lightweight execution unit sharing the process's memory/resources
CCannot be scheduled by the OS
DAlways requires its own separate processor
Answer is hidden
Question 43 of 84Real-Time Operating & Control System

Multitasking on a single processor is achieved through:

ATrue simultaneous execution of all tasks
BRapid time-slicing between tasks, giving the appearance of concurrency
CPhysically adding more processors
DDisabling the scheduler
Answer is hidden
Question 44 of 84Real-Time Operating & Control System

Multiprocessing differs from multitasking in that multiprocessing involves:

AA single processor time-slicing tasks
BMultiple processors executing tasks truly simultaneously
CNo task execution at all
DOnly software simulation of parallelism
Answer is hidden
Question 45 of 84Real-Time Operating & Control System

Rate-Monotonic scheduling assigns task priority based on:

ATask arrival order only
BThe task's period (fixed priority, shorter period = higher priority)
CRandom assignment
DThe amount of memory a task uses
Answer is hidden
Question 46 of 84Real-Time Operating & Control System

A semaphore in a real-time OS is used to:

AIncrease processor clock speed
BSynchronize access to shared resources between tasks
CCompile source code
DReplace the need for a scheduler
Answer is hidden
Question 47 of 84Real-Time Operating & Control System

A device driver's primary role is to:

AReplace the operating system entirely
BProvide a standard interface between the OS/application and specific hardware
CPerform task scheduling
DOnly manage memory allocation
Answer is hidden
Question 48 of 84Real-Time Operating & Control System

An open-loop control system is characterized by:

AOutput being fed back to correct the input
BNo feedback of output to influence the control action
CAutomatic disturbance compensation
DContinuous error correction
Answer is hidden
Question 49 of 84Real-Time Operating & Control System

A closed-loop (feedback) control system compares:

ANothing; it has no comparison mechanism
BThe measured output with a desired reference, using the error to adjust control action
COnly two open-loop systems against each other
DThe input against itself only
Answer is hidden
Question 50 of 84Real-Time Operating & Control System

Earliest-Deadline-First (EDF) is a scheduling algorithm that assigns priority based on:

AA fixed priority set at design time
BWhich task's deadline is soonest, dynamically
CRandom selection
DMemory usage of each task
Answer is hidden
Question 51 of 84Hardware Description Language & IC Technology

VHDL is primarily used to:

AWrite general-purpose application software
BDescribe the structure and behavior of digital hardware for simulation/synthesis
CManage databases
DCompile C programs
Answer is hidden
Question 52 of 84Hardware Description Language & IC Technology

In a VHDL design, the entity primarily defines:

AThe internal behavior of the circuit
BThe interface: input/output ports
CThe clock frequency only
DThe physical chip layout
Answer is hidden
Question 53 of 84Hardware Description Language & IC Technology

In a VHDL design, the architecture describes:

AOnly the port list
BThe internal behavior/structure implementing the entity's interface
CThe compiler settings
DThe operating system used
Answer is hidden
Question 54 of 84Hardware Description Language & IC Technology

Which VHDL description style describes a circuit as an interconnection of components?

ABehavioral
BDataflow
CStructural
DProcedural
Answer is hidden
Question 55 of 84Hardware Description Language & IC Technology

Overflow in a VHDL arithmetic operation occurs when:

AThe result fits perfectly within the bit width
BThe result exceeds the representable range of the chosen bit width
CNo arithmetic operation is performed
DThe clock signal is disabled
Answer is hidden
Question 56 of 84Hardware Description Language & IC Technology

Combinational logic in VHDL is typically modeled using:

AA process sensitive only to a clock edge
BConcurrent signal assignments or a process with a full input sensitivity list
COnly sequential (clocked) processes
DExternal simulation software only
Answer is hidden
Question 57 of 84Hardware Description Language & IC Technology

Sequential logic in VHDL is typically modeled using a process sensitive to:

AAll input signals only
BA clock edge (e.g. risingedge(clk))
CNo signals at all
DOnly the reset signal
Answer is hidden
Question 58 of 84Hardware Description Language & IC Technology

Pipelining in a VHDL design is implemented by:

ARemoving all clocked processes
BInserting register stages between combinational blocks
CUsing only combinational logic with no registers
DDisabling the clock entirely
Answer is hidden
Question 59 of 84Hardware Description Language & IC Technology

The dataflow style of VHDL description primarily uses:

AComponent instantiation only
BConcurrent signal assignments to describe signal flow
COnly behavioral algorithms with loops
DExternal hardware only, no code
Answer is hidden
Question 60 of 84Hardware Description Language & IC Technology

stdlogic and signed/unsigned vectors in VHDL are examples of:

AProgramming language keywords unrelated to hardware
BData types used to represent bits and numbers for modeling hardware signals
CClock signals only
DSimulation software tools
Answer is hidden
Question 61 of 84Computer Networks

Which feature of IPv6 is NOT supported (unlike IPv4)?

AUnicast
BMulticast
CBroadcast
DAnycast
Answer is hidden
Question 62 of 84Computer Networks

What is the maximum length of a hostname?

A255 characters
B128 characters
C64 characters
D512 characters
Answer is hidden
Question 63 of 84Computer Networks

Which OSI layer is responsible for process-to-process (end-to-end) communication?

ANetwork Layer
BTransport Layer
CSession Layer
DApplication Layer
Answer is hidden
Question 64 of 84Computer Networks

Which cable type is used to directly connect two routers without a switch?

ACrossover cable
BStraight-through cable
CRollover cable
DCoaxial cable
Answer is hidden
Question 65 of 84Computer Networks

In hierarchical routing, each autonomous domain (cluster) is called a:

AGateway
BRegion
CNode
DZone
Answer is hidden
Question 66 of 84Computer Networks

FTP uses how many TCP connections?

A1
B2
C3
D4
Answer is hidden
Question 67 of 84Computer Networks

Heavy network traffic that slows down response time is called:

ACongestion
BCollision
CDeadlock
DLatency
Answer is hidden
Question 68 of 84Computer Networks

The default port number for HTTP is:

A21
B80
C443
D25
Answer is hidden
Question 69 of 84Computer Networks

Which protocol is used for sending email from a client to a mail server?

AIMAP
BPOP3
CSMTP
DFTP
Answer is hidden
Question 70 of 84Computer Networks

What is the loopback address in IPv4?

A127.0.0.1
B192.168.0.1
C255.255.255.255
D0.0.0.0
Answer is hidden
Question 71 of 84Computer Networks

What is the network address of 192.10.16.32 with subnet mask /25?

A192.10.16.32
B192.10.16.0
C192.10.16.128
D192.10.0.0
Answer is hidden
Question 72 of 84Computer Networks

What is the Network ID of 203.17.10.7 with a /24 subnet mask?

A203.17.0.0
B203.17.10.0
C203.17.10.7
D203.0.0.0
Answer is hidden
Question 73 of 84Computer Networks

Which function is NOT performed at the Transport Layer?

ASegmentation and reassembly
BFlow control
CRouting
DError detection
Answer is hidden
Question 74 of 84Computer Networks

CDMA technology allows multiple users to:

AUse different frequency bands
BShare the same channel simultaneously using unique codes
CTake turns in time slots
DOperate on wired networks only
Answer is hidden
Question 75 of 84Computer Networks

A packet filter firewall operates at which OSI layer?

ALayer 2 (Data Link)
BLayer 3 (Network)
CLayer 4 (Transport)
DLayer 7 (Application)
Answer is hidden
Question 76 of 84Computer Networks

The most time-critical real-time network application is:

AEmail
BFile transfer
CInternet telephone (VoIP)
DWeb browsing
Answer is hidden
Question 77 of 84Computer Networks

A proxy server is implemented at which OSI layer?

AApplication Layer
BTransport Layer
CNetwork Layer
DData Link Layer
Answer is hidden
Question 78 of 84Computer Networks

The correct order of network types from smallest to largest geographic scope is:

ALAN < PAN < MAN < WAN
BPAN < LAN < MAN < WAN
CLAN < MAN < PAN < WAN
DPAN < WAN < LAN < MAN
Answer is hidden
Question 79 of 84Computer Networks

The RIP routing protocol uses which metric to determine the best path?

ABandwidth
BDelay
CHop count
DCost
Answer is hidden
Question 80 of 84Computer Networks

In RIP, a hop count of 16 means:

A16 routers away
BNetwork is unreachable
CMaximum allowed path
DDirect connection
Answer is hidden
Question 81 of 84Computer Networks

The IEEE standard for Ethernet is:

AIEEE 802.11
BIEEE 802.3
CIEEE 802.15
DIEEE 802.1
Answer is hidden
Question 82 of 84Computer Networks

Distance vector routing protocols use which algorithm to compute shortest paths?

ADijkstra's algorithm
BBellman-Ford algorithm
CFloyd-Warshall algorithm
DA* algorithm
Answer is hidden
Question 83 of 84Computer Networks

10Base5 Ethernet supports a maximum segment length of:

A100 m
B185 m
C500 m
D1000 m
Answer is hidden
Question 84 of 84Computer Networks

A typical LAN covers a geographic scope of up to:

A10 m
B1 km
C50 km
D500 km
Answer is hidden
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